Reconfigurable Shared Memory for Dynamic Dedicated Cache Allocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing processor-based systems face inefficiencies due to underutilization of dedicated memory resources, particularly in applications requiring varying memory sizes, leading to 'dark silicon' and increased die area.
Innovation Solution
A reconfigurable shared memory system that includes dedicated, general, and reconfigurable memory components, allowing dynamic reconfiguration of the reconfigurable memory as part of either the dedicated or general memory space based on application needs, optimizing memory utilization and reducing die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated memory is allocated to a particular client (e.g., GPU) to ensure fast access and meet scan-out deadlines, then memory access speed and reliability are improved, but memory utilization efficiency deteriorates due to underutilization when the client does not require the full dedicated memory size
Solution Approach 1:
The patent implements a reconfigurable memory system where the boundary between dedicated memory and general memory can be dynamically adjusted. The dedicated memory portion is configurable via control logic to match the actual memory requirements of the client (e.g., GPU), allowing the system to transition from a static dedicated memory allocation to a dynamic configuration that adapts to varying workload demands, thereby improving utilization efficiency while maintaining fast access speeds when needed.
Solution Approach 2:
The patent creates a multi-functional memory system where the same physical memory resources can serve both as dedicated memory for specific clients and as general memory for other clients, depending on the configuration. The reconfigurable memory architecture allows the memory to be universally accessed by different clients based on runtime requirements, eliminating the need for separate dedicated and shared memory pools and improving overall system efficiency.
2Loss of time
If dedicated memory is allocated to ensure fast access for specific applications, then access latency is reduced, but die area increases due to allocation of memory that may not be fully utilized
Solution Approach 1:
The patent employs dynamic configuration of memory boundaries to optimize the balance between access latency and die area. By making the dedicated memory portion configurable, the system can allocate exactly the amount of memory needed for each application, avoiding the waste of allocating excessive dedicated memory that would increase die area without providing proportional performance benefits. The dynamic adjustment ensures that fast access is provided only for the actual memory requirements.
Solution Approach 2:
The patent changes the parameter of memory allocation size from a fixed value to a configurable value. The dedicated memory portion can be adjusted based on the specific requirements of different applications, allowing the system to optimize the trade-off between access latency and die area for each workload. This parameter change enables the system to minimize die area while maintaining low latency when fast access is actually required.
3Productivity
If reconfigurable memory is added to allow dynamic allocation between dedicated and general memory space, then memory utilization efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into a dedicated memory portion and a general memory portion, with a configurable boundary between them. The reconfiguration capability is implemented through control logic that can adjust the boundary based on runtime requirements. This segmentation approach allows the system to maintain relatively simple structures for each memory portion while adding only the necessary control mechanisms for reconfiguration, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The patent introduces control logic as an intermediary component that manages the reconfiguration between dedicated and general memory portions. This intermediary handles the complexity of memory management, boundary adjustment, and client routing, isolating the complexity from the core memory structures. By concentrating the reconfiguration functionality in a dedicated control unit, the patent minimizes the complexity increase while achieving improved memory utilization efficiency.
Data Source
AI summary
Reconfigurable shared memory systems, and related processor-based systems and methods are disclosed. The reconfigurable shared memory system can be included in a processor-based system to provide memory for data storage. In exemplary aspects, the reconfigurable shared memory system not only includes the dedicated memory and the general memory (e.g., system cache memory), but also includes a reconfigurable memory. The reconfigurable memory can be configured as either part of addressable memory space of the dedicated memory if an application requires such additional dedicated memory, and/or configured as part of the addressable memory space of the general memory to provide additional memory to other clients for increased processing performance if such reconfigurable memory is not needed as part of the dedicated memory. The dedicated memory does not have to be sized to the worst-case size requirements of a given application.