Reconfigurable Memory Controller Multiplexing Modes
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Solution Overview
Problem
Existing memory systems face communication performance degradation due to differences in signaling rates and communication formats between various types of memory devices, such as DRAM and flash memory, when using a traditional double-data-rate-style interface on multi-drop command/address and data links.
Innovation Solution
A reconfigurable memory controller that switches between shared-link and dedicated-link operating modes, using spatial multiplexing and time multiplexing respectively, to maintain communication performance across different memory devices by adjusting the configuration of command/address, data, and clock links based on the specific memory configuration and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a traditional double-data-rate-style interface is used on multi-drop links to communicate with flash memory, then the number of interface pins is minimized, but signal integrity and communication performance are degraded
Solution Approach 1:
The interface circuit is designed to be reconfigurable, dynamically switching between shared-link mode and dedicated-link mode based on the type of memory device being accessed. This dynamic reconfiguration allows the system to optimize signal integrity for flash memory by using dedicated links when needed, while still minimizing pin count through shared-link mode when accessing DRAM
Solution Approach 2:
The same physical communication links are designed to serve multiple functions: they can operate as shared command/address and data links when accessing DRAM, and as dedicated command/address, data, and clock links when accessing flash memory. This multi-functionality eliminates the need for separate dedicated links for flash memory, reducing the overall pin count while maintaining signal integrity
2Device complexity
If different types of memory devices with different signaling rates are communicated using a minimum number of interface pins, then cost and size constraints are satisfied, but communication performance degrades due to signal integrity issues
Solution Approach 1:
The interface circuit reconfigures its operational mode dynamically based on the target memory device type. When flash memory is detected, the circuit switches to dedicated-link mode with appropriate signaling rate adjustments, ensuring optimal communication performance. When DRAM is detected, it operates in shared-link mode, maintaining high productivity through efficient time-multiplexed communication
Solution Approach 2:
The system changes operational parameters including signaling rates, link configurations, and communication protocols based on the detected memory device type. This parameter adaptation allows the same physical interface to achieve optimal communication performance with both DRAM and flash memory despite their different signaling rate requirements
3Reliability
If a reconfigurable interface circuit is implemented to support both shared-link and dedicated-link modes, then communication performance with different memory types is maintained, but device complexity increases
Solution Approach 1:
The interface circuit implements a universal design that can operate in multiple modes (shared-link and dedicated-link) using the same physical infrastructure. This multi-functionality is achieved through configurable multiplexers and mode-select logic that route signals appropriately based on the operational mode, avoiding the need for completely separate circuit implementations for different memory types
Data Source
AI summary
Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.