Reconfigurable Memory Controller Using Partial Reconfiguration
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Solution Overview
Problem
Programmable logic devices face a tradeoff between runtime programmability and system performance due to increased logic on critical timing paths, which affects the implementation of specific memory controller functions.
Innovation Solution
A reconfigurable memory controller circuit with a processor that initially configures programmable logic and interconnect resources with a reference configuration dataset to implement a general memory controller, and then selectively reconfigures specific portions using partial reconfiguration datasets based on memory arrangement characteristics, allowing for various memory controller implementations without impacting performance or increasing storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the FPGA is configured to be programmable to implement a specific memory controller function, then adaptability is improved, but system performance deteriorates due to increased logic along critical timing paths
Solution Approach 1:
The configuration data is segmented into two parts: a reference configuration data-set that remains fixed to maintain critical timing paths, and a partial reconfiguration data-set that can be dynamically updated to implement different memory controller functions. This segmentation allows the system to maintain high performance while gaining adaptability through selective reconfiguration of non-critical portions.
Solution Approach 2:
The reference configuration data-set is prepared in advance and loaded into the FPGA's configuration memory cells before operation. This preliminary configuration establishes the critical timing paths that ensure high performance. Subsequent partial reconfiguration data-sets can then be applied without disrupting these pre-established critical paths, enabling adaptability without performance degradation.
2Adaptability or versatility
If multiple specific memory controller functions are implemented using full configuration data-sets, then adaptability is improved, but storage space increases
Solution Approach 1:
The invention extracts only the differing portions between the reference configuration and each specific memory controller configuration into separate partial reconfiguration data-sets. Instead of storing complete configuration data-sets for multiple functions, the system stores a single reference configuration and multiple small partial data-sets that can be selectively applied, dramatically reducing storage requirements while maintaining full functionality.
Solution Approach 2:
A single reference configuration data-set serves as a universal base that supports multiple specific memory controller functions. By combining this universal reference with different partial reconfiguration data-sets, the system can implement various specific functions without needing separate complete configuration files for each, achieving multi-functionality with minimal storage overhead.
Data Source
AI summary
A circuit controls a memory arrangement and includes an array of programmable resources and interconnect resources, a reconfiguration port, and a processor. The programmable resources and interconnect resources in the array are initially configured with a reference configuration data-set. The reference configuration data-set configures the programmable resources and interconnect resources to implement a general memory controller. The processor obtains a characteristic of the memory arrangement and selects a particular partial reconfiguration data-set based on the characteristic of the memory arrangement. The processor reconfigures the programmable resources and interconnect resources in the array via the reconfiguration port. The processor reconfigures the programmable resources and interconnect resources with the particular partial reconfiguration data-set. The particular partial reconfiguration data-set partially reconfigures the programmable resources and interconnect resources to implement a portion of a specific memory controller that differs from the general memory controller.