Reconfigurable Memory Device with Extra Arrays for Flexible Data Storage

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Solution Overview

Problem

Conventional memory devices have fixed page sizes, limiting their ability to store extra data efficiently, especially for applications requiring flexible storage configurations.

Innovation Solution

A memory device with reconfigurable extra arrays, allowing for the storage of extra data alongside standard array data, with two access modes for reading and writing operations, enabling flexible data management through specific command codes and access sequences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fixed page sizes are used in conventional memory devices, then the memory structure is simple and easy to manufacture, but the ability to store extra data efficiently is limited

Engineering Contradiction:
Improvestorage flexibilityVSAvoidmemory structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory device is segmented into two distinct types of memory blocks: array blocks for storing array data and extra array blocks for storing extra data. Each block type can be independently managed and accessed, allowing flexible storage configurations without complicating the overall memory structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory device is designed to perform multiple functions through a unified structure that can store both array data and extra data. The same basic memory cell structure serves dual purposes by being organized into different block types, maintaining manufacturing simplicity while enhancing storage versatility

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If extra arrays are added to store additional data, then storage capacity and flexibility are improved, but the read/write operation complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess operation simplicity
Core Design Contradiction:
Quantity of substanceVSEase of operation

Solution Approach 1:

A logic unit acts as an intermediary between the controller and the memory blocks. It automatically determines whether to access array blocks or extra array blocks based on the command code, shielding the user from the complexity of dual-block management while enabling enhanced storage capacity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The memory access mode is made dynamic through different command codes (first command code for array data, second command code for extra data). The logic unit adapts the access sequence based on the command received, allowing flexible storage capacity expansion without requiring complex user-side access logic

Inventive Principle:
Principle #15Dynamics

3Reliability

If sequential reading of array data and extra data is implemented, then data security and error correction are enhanced, but the read operation time increases

Engineering Contradiction:
Improvedata securityVSAvoidread operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Error correction and data security measures are integrated into the sequential read operation through preliminary actions performed by the logic unit. The logic unit prepares and executes error correction codes during the sequential access process, enhancing reliability without requiring separate post-processing steps that would further increase read time

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3057100B1Memory device and operating method of same
Publication Date: 2017.11.22 MACRONIX INTERNATIONAL CO LTD
  • EP3057100B1 patent drawingFigure 1
  • EP3057100B1 patent drawingFigure 2
  • EP3057100B1 patent drawingFigure 3A~3B

AI summary

A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.