Reconfigurable Memory Interface Circuit ATPG Scan Chain
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Solution Overview
Problem
The inclusion of scan latches in memory interfaces for automatic test pattern generation (ATPG) scans increases area overhead, necessitating a method to enable ATPG scans without incorporating these latches.
Innovation Solution
A reconfigurable memory interface circuit utilizing multiplexers and latches that operate as master and slave flip-flops in functional and ATPG scan modes, allowing for ATPG scans without dedicated scan latches, by splitting the scan into two ATPG scans to test different sets of functional inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan latches are included in the memory interface circuit for ATPG scans, then ATPG scan capability is enabled, but area overhead of the memory increases
Solution Approach 1:
The existing latches in the memory interface circuit are made multi-functional by adding control logic. These latches can operate in two modes: functional mode for normal memory operations and ATPG scan mode for testing. The control logic selectively configures the latches based on the operational mode, allowing the same hardware resources to serve both functional and testing purposes without requiring dedicated scan latches.
Solution Approach 2:
The latch configuration is made dynamic through control signals that can reconfigure the latches between functional mode and ATPG scan mode. In functional mode, latches operate as standard memory interface elements. In ATPG scan mode, the control logic reconfigures them to form scan chains, enabling test operations. This dynamic reconfiguration allows a single set of latches to adapt to different operational requirements.
2Area of stationary object
If dedicated scan latches are removed to reduce area overhead, then area overhead is reduced, but ATPG scan capability is lost
Solution Approach 1:
The existing latches in the memory interface circuit are made self-sufficient for ATPG scanning by adding control logic that enables them to function as scan elements. Instead of requiring external dedicated scan latches, the memory interface latches themselves perform the scanning function when configured appropriately. The control logic enables these latches to capture, hold, and shift test data internally, making the system self-service for testing purposes.
3Adaptability or versatility
If scan chains are split into shorter scans to accommodate test equipment limitations, then test equipment compatibility is improved, but test time increases
Solution Approach 1:
The long scan chain is segmented into multiple shorter scan chains or segments that can be tested independently. This segmentation allows the test equipment to handle each segment separately within its length limitations. The control logic manages the segmentation by selectively activating different latch groups for different test segments, enabling comprehensive testing of the entire memory while accommodating equipment constraints.
Solution Approach 2:
The testing is performed in periodic cycles where each cycle tests a specific segment of the scan chain. The control logic orchestrates periodic activation of different latch segments, allowing test equipment to process manageable portions sequentially. This periodic approach to testing entire scan chains through segmented cycles reduces the burden on test equipment while maintaining comprehensive coverage.
Data Source
AI summary
A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.