Reconfigurable Memory Interface Channel for Latency and Throughput
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Solution Overview
Problem
The number of channels in semiconductor-based storage devices is limited by parasitic components and connection complexity, hindering efficient access to high-capacity memory devices.
Innovation Solution
A reconfigurable memory interface system that includes a control sub-channel and multiple data sub-channels, allowing the memory controller to switch between modes for optimized data transfer, either synchronizing all sub-channels for high throughput or using them independently for low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of channels is increased to improve memory access rate, then productivity is improved, but device complexity increases due to parasitic components and connection complexity
Solution Approach 1:
The patent implements a reconfigurable channel that can dynamically switch between different operational modes (first mode and second mode) based on access patterns. The channel adapts its configuration to optimize performance for different scenarios: synchronous operation for high throughput and independent operation for low latency, thereby improving memory access rate without requiring multiple fixed channels that would increase connection complexity
Solution Approach 2:
The reconfigurable channel serves multiple functions by being able to operate in different modes. A single channel structure is designed to handle both synchronous data transfer (where multiple sub-channels work together) and independent data transfer (where sub-channels operate separately), eliminating the need for separate dedicated channels for different access patterns and reducing overall connection complexity
2Productivity
If the number of channels is increased to improve memory access rate, then productivity is improved, but parasitic components increase
Solution Approach 1:
The reconfigurable channel dynamically adjusts its operational characteristics based on access patterns. By switching between synchronous mode (for high throughput) and independent mode (for low latency), the system achieves high memory access rates without requiring a large number of permanently active channels, thereby minimizing parasitic components associated with unused or underutilized channel infrastructure
3Speed
If sub-channels are used independently to reduce latency, then speed is improved, but device complexity increases
Solution Approach 1:
The control circuit dynamically selects between synchronous and independent sub-channel operation modes based on access patterns. For latency-sensitive operations, the system switches to independent mode where sub-channels operate separately, achieving lower latency. The control circuit manages this switching through standardized control signals, preventing exponential growth in control complexity despite the reconfigurable nature of the channel
Data Source
AI summary
A method of communicating with a memory device through a plurality of sub-channels and a control sub-channel includes; setting a first mode or a second mode. In the first mode, writing or reading first data corresponding to a command synchronized to the control sub-channel through the plurality of sub-channels, and in the second mode, independently writing or reading second data and third data respectively corresponding to different commands synchronized to the control sub-channel through the plurality of sub-channels.