Reconfigurable In-Memory LUT Logic for Parallel Computing Pipelines
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Solution Overview
Problem
Existing computer systems face challenges in improving throughput while avoiding exorbitant costs and energy consumption by increasing the number of processing cores, such as GPUs, which often lead to inefficient computational solutions.
Innovation Solution
Implementing reconfigurable processing-in-memory (PIM) logic using look-up tables (LUTs) in memory devices, which include logic arrays and control blocks to manage computations, enabling various computational pipelines like superscalar and hardware neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing cores is increased to improve throughput, then computational performance is improved, but energy consumption and cost increase excessively
Solution Approach 1:
The patent combines memory storage and processing logic into a single integrated structure where look-up tables are stored within the memory device itself. This merging eliminates the need for separate processing cores while enabling parallel computation through simultaneous access to multiple LUT entries, thereby improving throughput without proportionally increasing energy consumption.
Solution Approach 2:
The memory device is designed to perform multiple functions: it serves as both storage medium and computational unit. The look-up tables can be configured to implement various logical operations (AND, OR, NAND, NOR, XOR, etc.), allowing the same hardware structure to adapt to different computational tasks without requiring dedicated processing cores for each function.
2Productivity
If specialized processors like ASICs or GPUs are used to improve computational performance, then throughput is improved, but cost increases excessively
Solution Approach 1:
The patent creates a universal computing platform where the same memory device can be configured to perform different logical operations by loading appropriate look-up tables. This eliminates the need for costly specialized processors for each specific computational task, as the reconfigurable LUT-based system can adapt to various algorithms and workloads using standard memory hardware.
Solution Approach 2:
The patent uses look-up tables that store pre-computed results of logical operations. Instead of implementing complex processing logic in hardware, the system copies the desired computational behavior into tabular form within memory, allowing efficient retrieval and execution of computational functions through simple memory access operations rather than expensive specialized circuitry.
3Ease of manufacture
If reconfigurable PIM logic using LUTs is implemented to provide cost-effective parallelism, then cost is reduced, but device complexity increases
Solution Approach 1:
The patent divides the computational function into discrete look-up table entries, each representing a specific logical operation or intermediate computation result. This segmentation allows the complex task of parallel computation to be broken down into manageable table lookups that can be executed simultaneously, reducing the apparent complexity of the control logic while maintaining high performance.
Solution Approach 2:
The look-up table acts as an intermediary between the simple memory access operation and the complex logical computation. Instead of directly implementing complex logic circuits, the system uses the LUT as a mediator that translates simple address inputs into computed output values, thereby reducing device complexity while enabling sophisticated parallel computations.
Data Source
AI summary
An example system implementing a processing-in-memory pipeline includes: a memory array to store a plurality of look-up tables (LUTs) and data; a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs; and a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data.