Reconfigurable Multi-Core Processor With Cognitive On-Chip Network
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Solution Overview
Problem
Current microprocessor designs face challenges in achieving high energy efficiency and adaptability for multi-purpose devices, as they often require a trade-off between cost, power consumption, and programmability, with existing solutions like ASICs, GPMs, and FPGAs having limitations in hardware efficiency and adaptability.
Innovation Solution
A reconfigurable and programmable multi-core processor with a self-routing cognitive on-chip network and programmable elements, allowing for flexible data routing and operation sequencing, along with a method for efficiently partitioning and programming software to optimize hardware resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASIC is used for specific applications, then hardware efficiency is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements a multi-core processor architecture where each core can be dynamically configured to perform different functions. The processor supports multiple instruction sets and can switch between different operational modes (integer, floating-point, SIMD, VLIW) to adapt to various application requirements while maintaining high hardware efficiency through specialized execution units.
Solution Approach 2:
The processor employs dynamic configuration capabilities where instruction pipelines, execution units, and data paths can be reconfigured at runtime. The architecture allows dynamic switching between different pipeline stages, instruction formats, and operational modes based on the specific task requirements, enabling the system to optimize performance for different workloads without sacrificing adaptability.
2Adaptability or versatility
If GPM is programmed using high-level languages, then adaptability is improved, but hardware efficiency deteriorates
Solution Approach 1:
The patent divides the processor into multiple independent cores, each capable of executing different instruction sets and operating modes. This segmentation allows the system to allocate specific cores for high-level language execution while other cores handle specialized operations, thereby maintaining both programming flexibility and hardware efficiency simultaneously.
Solution Approach 2:
The architecture introduces a layered instruction set architecture that acts as an intermediary between high-level programming languages and the underlying hardware. The processor supports multiple instruction sets (including VLIW and SIMD) that bridge the gap between high-level language abstractions and efficient hardware execution, allowing developers to write portable code while achieving optimized performance through compiler-generated specialized instructions.
3Adaptability or versatility
If FPGA is used for adaptability, then programmability is improved, but power consumption and cost deteriorate
Solution Approach 1:
The patent implements specialized execution units within each processor core that are optimized for specific operation types (integer arithmetic, floating-point operations, SIMD processing, VLIW execution). These localized specialized units provide FPGA-like adaptability only where needed, rather than requiring the entire processor to be reconfigurable, thereby reducing overall power consumption while maintaining programming flexibility through software-controlled configuration.
Data Source
AI summary
A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, Time Fields are added to the instruction format for all programming units that specify the number of clock cycles for which only one fetched and decoded instruction will be executed.