Reconfigurable Multi-Stack Inductor for Tunable RF Circuits
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Solution Overview
Problem
Existing on-chip inductor designs face challenges in achieving a high quality factor, self-resonance frequency, and tunability while occupying minimal chip area, as they require multiple inductors that occupy the same real estate, limiting their reconfigurability and frequency band selection capabilities.
Innovation Solution
A reconfigurable multi-stack inductor structure is formed within a semiconductor structure, utilizing a first and second inductor structure in different metal layers with ground shielding structures that can be electrically coupled or floated to generate varying inductance values, allowing for increased tuning range and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple inductor structures are coupled to generate different inductance values, then inductance tunability is improved, but chip area occupancy remains the same
Solution Approach 1:
The patent transitions from planar inductor arrangements to a three-dimensional stacked configuration where inductors are placed in different metal layers (first metal layer and second metal layer). This vertical stacking enables multiple inductors to occupy the same horizontal footprint while providing distinct inductance values through inter-layer coupling, thereby achieving inductance tunability without increasing chip area.
Solution Approach 2:
The patent implements a nested structure where the second inductor structure is positioned directly above the first inductor structure in adjacent metal layers. The ground shielding structures are nested within the same horizontal footprint as the inductor structures, with the second ground shielding structure located above the first. This nesting arrangement allows multiple functional elements to coexist within a compact volume, maximizing space utilization while maintaining electrical isolation and functionality.
2Object-affected harmful factors
If ground shielding structures are coupled to ground, then shielding effectiveness is improved, but inductance value is reduced
Solution Approach 1:
The patent implements switchable ground connections for the ground shielding structures, allowing the system to dynamically transition between different operational states. Switches can connect or disconnect the ground shielding structures from ground potential, enabling the inductor to switch between configurations with different inductance values. This dynamic reconfiguration allows optimization of inductance value while maintaining shielding effectiveness when needed.
Solution Approach 2:
The patent changes the electrical state parameter of the ground shielding structures by switching between grounded and floating conditions. When the ground shielding structures are connected to ground, they provide effective electromagnetic shielding but reduce the inductance value. When disconnected (floating), the inductance value increases. This parameter change enables adaptive optimization of the inductor characteristics based on circuit requirements.
3Area of stationary object
If inductor structures are placed in different metal layers, then chip area footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes existing multi-layer metal infrastructure of CMOS technology to implement stacked inductors. The same fabrication processes used for creating multiple metal interconnect layers are leveraged to form the inductor structures and ground shielding structures. Switches and coupling mechanisms utilize standard CMOS device components, making the implementation compatible with existing manufacturing capabilities without requiring specialized process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a 40% increased tuning range with a reduced chip footprint, enabling configurable inductance values across different frequencies, enhancing the performance of CMOS RF circuit designs.
Implementation Method 1
a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure
Data Source
AI summary
A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.