Reconfigurable Multiprocessor Architecture for Energy Efficient Microprocessors
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Solution Overview
Problem
General-purpose microprocessors face a performance growth retardation due to power limitations, as they fail to keep pace with the increase in transistors, leading to a need for improved energy efficiency without increasing power requirements, while maintaining flexibility similar to application-specific integrated circuits (ASICs).
Innovation Solution
The Stella SoC implements software-controlled optimization of hardware architecture, creating a virtual ASIC by using a hierarchy of programmable switches to interconnect compute and storage blocks, forming dynamic cores with variable clock rates and data transfer mechanisms, allowing for near-ASIC power efficiency with full programming flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If general-purpose microprocessors increase transistor density to improve performance, then the number of transistors increases, but clocking frequency growth slows due to power limitations
Solution Approach 1:
The patent implements dynamic reconfiguration of hardware architecture through programmable switches that can change connectivity between compute blocks, storage blocks, and interconnect structures. This allows the microprocessor to adapt its architecture dynamically based on workload requirements, optimizing performance for specific applications while managing power consumption effectively
Solution Approach 2:
The system changes architectural parameters such as data path width, compute block configuration, and interconnect topology through software-controlled reconfiguration. This enables the processor to optimize its operational parameters for different computational tasks, improving performance without proportionally increasing power consumption
2Use of energy by moving object
If ASICs are designed for specific applications to improve power efficiency, then power efficiency increases, but flexibility and programmability decrease
Solution Approach 1:
The patent creates a universal microprocessor architecture that can function as different specialized processors through software-controlled reconfiguration. The same physical hardware can be reconfigured to implement different computational patterns, data flow architectures, and interconnect structures, providing both the flexibility of programmability and the efficiency of application-specific designs
Solution Approach 2:
The system transitions from static ASIC architecture to dynamic reconfigurable architecture, allowing the hardware structure to change based on computational requirements. This enables the processor to adapt its connectivity and resource allocation dynamically, achieving application-specific efficiency while maintaining general-purpose programmability
3Adaptability or versatility
If data is transferred over long distances in general-purpose microprocessors, then versatility is maintained, but energy consumption increases due to wire length
Solution Approach 1:
The patent implements local data transfer optimization by reconfiguring the interconnect structure to minimize wire lengths for specific computational patterns. The programmable switches can create locally-optimized data paths that reduce the physical distance data must travel, thereby reducing energy consumption while maintaining the ability to perform versatile computations through different configuration patterns
Data Source
AI summary
An SoC maintains the full flexibility of a general-purpose microprocessor while providing energy efficiency similar to an ASIC by implementing software-controlled virtual hardware architectures that enable the SoC to function as a virtual ASIC. The SoC comprises a plurality of “Stella” Reconfigurable Multiprocessors (SRMs) supported by a Network-on-a-Chip that provides efficient data transfer during program execution. A hierarchy of programmable switches interconnects the programmable elements of each of the SRMs at different levels to form their virtual architectures. Arithmetic, data flow, and interconnect operations are also rendered programmable. An architecture index” points to a storage location where pre-determined hardware architectures are stored and extracted during program execution. The programmed architectures are able to mimic ASIC properties such as variable computation types, bit-resolutions, data flows, and amount and proportions of compute and data flow operations and sizes. Once established, each architecture remains in place as long as needed.