Reconfigurable Neural Network Hardware Accelerator Instruction Decoder
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Solution Overview
Problem
Hardware accelerators for neural networks face limitations in supporting new neural network topologies and applications due to fixed instruction sets, which restrict their ability to perform evolving operations and adapt to changing neural network architectures.
Innovation Solution
A reconfigurable neural network hardware accelerator with a programmable instruction decoder, instruction schema mapping table, and hardware execution engine, allowing for flexible opcode and operand definitions, and support for various memory access modes, enabling the execution of a wide range of operations without altering the accelerator's design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed instruction set is used in hardware accelerators, then the device complexity is reduced and manufacturing is easier, but the adaptability to new neural network topologies and applications deteriorates
Solution Approach 1:
The instruction decoder is made reconfigurable through programmable logic, allowing the opcode definitions and operand interpretations to be dynamically changed via configuration data. This enables the same hardware accelerator to adapt to different neural network topologies and applications by loading appropriate configuration sets, resolving the contradiction between fixed architecture and evolving requirements.
Solution Approach 2:
The patent changes the parameters of the instruction set by allowing opcode bit lengths, operand bit lengths, and operand offsets to be variable rather than fixed. Configuration data defines these parameters, enabling the hardware accelerator to support different neural network operations by modifying instruction encoding parameters without changing the underlying hardware architecture.
2Adaptability or versatility
If the hardware accelerator supports multiple memory access modes, then the operational flexibility is improved, but the device complexity increases
Solution Approach 1:
The memory access circuit is designed with multi-functionality to support multiple access modes including sequential access, random access, and banked access. By integrating these different access patterns into a single unified circuit design that can be configured through control signals and operands, the patent achieves operational flexibility without proportionally increasing device complexity.
3Adaptability or versatility
If the instruction set is expanded to support new operations, then the adaptability is improved, but the ease of operation deteriorates due to increased instruction decoding complexity
Solution Approach 1:
Configuration data serves as an intermediary between the instruction stream and the instruction decoder. The configuration data contains predefined opcode definitions and operand interpretations that act as a mapping layer, translating variable-length and variable-format instructions into standardized internal operations. This intermediary structure simplifies the decoding process by providing a consistent lookup mechanism regardless of instruction format variations.
Data Source
AI summary
In one example, a hardware accelerator comprises: a programmable hardware instruction decoder programmed to store a plurality of opcodes; a programmable instruction schema mapping table implemented as a content addressable memory (CAM) and programmed to map the plurality of opcodes to a plurality of definitions of operands in a plurality of instructions; a hardware execution engine; and a controller configured to: receive an instruction that includes a first opcode of the plurality of opcodes; control the hardware instruction decoder to extract the first opcode from the instruction; obtain, from the instruction schema mapping table and based on the first opcode, a first definition of a first operand; and forward the instruction and the first definition to the hardware execution engine to control the hardware execution engine to extract the first operand from the instruction based on the first definition, and execute the instruction based on the first operand.