Reconfigurable Neural Network Circuit for Inline Packet Analysis
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Solution Overview
Problem
Existing deep learning techniques for network analysis based on neural networks are inadequate for real-time analysis due to the need for large packet volumes, leading to delayed detection of network intrusions and inadequate protection.
Innovation Solution
A reconfigurable neural network circuit is employed for inline network analysis, allowing real-time processing of packets at line rate through adaptive configuration and computation, enabling efficient detection of network anomalies, intrusions, and congestion using a pipeline architecture that supports billions of packets per second.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of packets (over 10,000 packets) are applied to the neural network to determine network characteristics, then the accuracy of network anomaly detection is improved, but the response time increases significantly, making real-time protection impossible
Solution Approach 1:
The system performs preliminary actions by continuously maintaining a sliding window of recent packets and pre-computing statistical features (mean, variance, min, max) as packets arrive. This preliminary feature extraction and statistical computation enables the neural network to make accurate predictions based on a manageable number of recent packets rather than waiting for a large complete flow, thus achieving both accuracy and real-time response.
Solution Approach 2:
The system dynamically adapts the number of packets processed by implementing a sliding window mechanism that adjusts the effective packet count based on flow characteristics and time constraints. The window size and packet selection are dynamically adjusted to maintain optimal balance between having sufficient data for accurate neural network inference and maintaining real-time processing capability, resolving the contradiction between detection accuracy and response time.
2Productivity
If packets are processed in a traditional sequential manner, then processing simplicity is maintained, but throughput is limited and cannot achieve line rate processing
Solution Approach 1:
The packet processing system is segmented into distinct functional stages: packet arrival, feature extraction, statistical computation, neural network inference, and decision output. Each stage operates independently and can be optimized separately. The sliding window mechanism segments the packet stream into manageable recent packets, enabling parallel processing and achieving line rate throughput while maintaining architectural clarity through modular segmentation.
Solution Approach 2:
The system ensures continuous useful action by maintaining an ever-updating sliding window of recent packets and continuously computing statistical features as new packets arrive. This continuous feature extraction and statistical maintenance allows the neural network to receive updated inputs without interruption, enabling continuous high-speed processing at line rate while the background processes handle feature computation and window management.
Data Source
AI summary
Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a reconfigurable neural network circuit to determine an indication of a predicted network characteristic. In one aspect, the reconfigurable neural network circuit includes a control circuit to select a packet attribute or a flow attribute of a raw packet stream from a pipeline, and determine a configuration setting corresponding to the packet attribute or the flow attribute. The configuration setting may indicate a configuration of the reconfigurable neural network circuit to implement a neural network. In one aspect, the reconfigurable neural network circuit includes a storage to provide neural network parameters of the neural network, according to the configuration setting. In one aspect, the reconfigurable neural network circuit includes computational circuits to perform computations based on the neural network parameters from the storage to determine the indication of the predicted network characteristic.


