Reconfigurable PE Array for Gaussian Pyramid Construction
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Solution Overview
Problem
Conventional software-based SIFT algorithms are inadequate for meeting the demands of improved image clarity and real-time requirements due to high computational load and energy consumption in Gaussian pyramid construction, particularly due to mismatched data reading and writing speeds and lack of symmetry consideration in existing hardware acceleration methods.
Innovation Solution
A reconfigurable hardware acceleration method and system that utilizes a dual clock domain design, edge padding, and symmetry of the Gaussian convolution kernel to optimize Gaussian pyramid construction, including steps like storing pixel data in a line buffer, adjusting row order, determining edge padding, and performing time division multiplexing with reconfigurable processing elements to achieve efficient Gaussian pyramid and difference pyramid construction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fully parallel computing is used for Gaussian pyramid construction, then real-time performance is improved, but hardware overhead increases and hardware utilization rate decreases due to memory speed mismatch
Solution Approach 1:
The patent employs dynamic reconfiguration of processing elements (PEs) to adapt to different computational stages. PEs can be dynamically enabled or disabled based on the current pyramid level being processed, allowing the hardware to optimize its resource usage for each specific computation phase rather than maintaining fixed parallel structures throughout.
Solution Approach 2:
The patent implements periodic computation cycles where PEs are activated in stages corresponding to different pyramid levels. Each PE processes multiple pyramid levels sequentially with periodic activation, reducing the number of simultaneously active PEs and thereby lowering hardware overhead while maintaining real-time processing capability.
2Productivity
If fully parallel computing is used for Gaussian pyramid construction, then real-time performance is improved, but hardware utilization rate decreases due to computational unit idle time
Solution Approach 1:
The patent pre-loads pixel data into on-chip memory buffers before computation begins. This preliminary data preparation ensures that when PEs are activated, they immediately have the required data available, eliminating idle waiting time during computation and maximizing hardware utilization.
Solution Approach 2:
The patent implements a continuous data flow architecture where pixel data is continuously fed through the processing pipeline. As one PE completes its computation, the next PE is already ready with data, ensuring continuous useful action without idle periods and maintaining high hardware utilization throughout the real-time processing cycle.
3Reliability
If symmetry of Gaussian function is not considered, then computational completeness is maintained, but calculation amount and hardware overhead increase
Solution Approach 1:
The patent exploits the symmetry properties of the Gaussian function by implementing asymmetric computation strategies. Instead of performing complete symmetric convolutions, the system calculates only the necessary unique portions and mirrors the results, reducing calculation amount by approximately half while maintaining computational completeness and accuracy.
4Productivity
If edge padding is not considered during convolution, then computational speed is maintained, but output images suffer from distortion
Solution Approach 1:
The patent introduces edge padding as an intermediary layer around the input image before convolution operations. This padding layer prevents edge pixels from being distorted during convolution by providing artificial boundary pixels, thereby maintaining output image quality without significantly impacting computational speed since the padding is generated once and reused.
Data Source
AI summary
The disclosure discloses a reconfigurable hardware acceleration method and system for Gaussian pyramid construction and belongs to the field of hardware accelerator design. The system provided by the disclosure includes a static random access memory (SRAM) bank, a first in first out (FIFO) group, a switch network, a shift register array, an adder tree module, a demultiplexer, a reconfigurable PE array, and a Gaussian difference module. In the disclosure, according to the requirements of different scenarios and different tasks for the system, reconfigurable PE array resources can be configured to realize convolution calculations of different scales. The disclosure includes methods of fast and slow dual clock domain design, dynamic edge padding design, and input image partial sum reusing design.