Reconfigurable PE Arrays for Scalable Thread-Level Parallelism
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Solution Overview
Problem
Existing reconfigurable computing architectures, such as CGRA, are limited by loop-level parallelism and lack scalability in handling thread-level parallelism, while GPU architectures are not reconfigurable, necessitating a processor that can harness the capabilities of both for efficient and scalable parallel processing.
Innovation Solution
A processor design that incorporates a programmable processor array similar to CGRA, utilizing processing elements with vector arithmetic logic units, memory ports, and a sequencer to distribute configurations, allowing for thread-level parallelism and efficient data access through private and shared memory methods, with a gasket memory for temporary data storage and switch boxes for data switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CGRA architecture is used to achieve reconfigurability, then adaptability is improved, but thread-level parallelism capability deteriorates
Solution Approach 1:
The processor array is segmented into multiple independently configurable processing elements (PEs) that can be dynamically reconfigured to handle different thread-level parallelism workloads. Each PE can be individually programmed and configured, allowing the system to adapt to various computational patterns while maintaining high parallelism throughput.
Solution Approach 2:
The architecture implements dynamic reconfiguration capabilities where processing elements can change their operational mode and configuration during runtime. This allows the system to transition between different computational tasks and optimize for thread-level parallelism by dynamically allocating and configuring PEs based on workload requirements.
2Productivity
If GPU architecture is used to achieve thread-level parallelism, then productivity is improved, but adaptability deteriorates
Solution Approach 1:
The processing elements are designed with universal functionality that can execute multiple types of operations and be configured for different computational patterns. Each PE contains configurable functional units that can be programmed to perform various arithmetic, logic, and data manipulation operations, providing both high parallelism throughput and adaptability to different algorithms.
Solution Approach 2:
The architecture allows dynamic changing of operational parameters such as data path width, operation type, and configuration state of processing elements. This enables the system to optimize performance for specific thread-level parallelism workloads while maintaining the ability to reconfigure for different computational patterns, effectively combining GPU-like productivity with CGRA-like adaptability.
3Productivity
If PE array size is increased to improve parallelism, then productivity is improved, but device complexity increases
Solution Approach 1:
The processing elements are organized in a hierarchical nested structure where PEs are grouped into banks, which are further organized into arrays. This nested organization allows for scalable parallelism by enabling selective activation and configuration of different levels of the hierarchy, managing complexity through structured modularity while maintaining high parallelism capabilities.
Solution Approach 2:
The system dynamically adjusts operational parameters such as the number of active PEs, array dimensions, and configuration depth based on workload requirements. This parameter-based control allows the architecture to scale parallelism efficiently without proportionally increasing complexity, as the system can activate only the necessary number and type of PEs for each computational task.
Data Source
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AI summary
Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.