Reconfigurable PE Architecture With Dynamic Data-Driven Scheduling
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Solution Overview
Problem
Traditional reconfigurable architectures like FPGAs and CGRAs face limitations in flexibility, energy efficiency, and programming complexity, with static scheduling leading to suboptimal performance and increased latency due to point-to-point networks and complex routing.
Innovation Solution
A dynamic data-driven reconfigurable architecture (3DRA) that allows for flexible, all-to-all communication and dynamic execution, where processing elements (PEs) execute instructions only when operands are ready, reducing latency and simplifying mapping by using data broadcasting lines and FIFOs to manage operand availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If static placement and static issue scheduling is used, then routing complexity is reduced, but execution flexibility and performance are worsened
Solution Approach 1:
The patent implements dynamic issue scheduling where the issue schedule is generated at runtime based on actual operand availability, rather than being fixed at compilation time. This allows the system to adapt to dynamic events and optimize execution performance while maintaining simplified routing through static placement.
Solution Approach 2:
Each processing element autonomously determines when to issue instructions based on local knowledge of operand availability, eliminating the need for complex centralized scheduling. The processing elements self-coordinate through simple ready signals on the mesh network.
2Device complexity
If point-to-point network is used for connecting processing units, then routing path is simplified, but latency increases due to multi-hop traversal
Solution Approach 1:
The patent introduces a mesh network with crossbar switches as intermediaries between processing elements. This allows direct single-hop communication paths to be established dynamically, eliminating multi-hop traversal latency while maintaining the simplicity of point-to-point connections through the mesh infrastructure.
Solution Approach 2:
The patent transitions from a linear or hierarchical interconnection to a mesh network topology, adding spatial dimensions to the communication fabric. This enables multiple direct paths between processing elements, reducing the number of hops required for data transfer.
3Device complexity
If wires on mesh network are used only once per cycle, then routing contention is reduced, but data transfer efficiency is worsened
Solution Approach 1:
The patent implements early allocation of network resources by reserving wire usage rights before data transfer begins. Processing elements declare their intended data transfers in advance, allowing the mesh network to pre-configure switching paths and avoid contention during actual data movement.
Solution Approach 2:
The patent enables multiple data transfers to occur simultaneously across the mesh network by allowing wires to be reused in subsequent cycles once data has been successfully transmitted. This continuous utilization of network resources maximizes data transfer efficiency while maintaining manageable contention levels.
Data Source
AI summary
A computing circuit comprising a plurality of reconfigurable processing elements (PEs); data communication lines connecting an output port of each of the PEs with an input port of each other one of the PEs; wherein the computing circuit is configured to execute a data flow model by configuring at least a second subset of the plurality of PEs to perform a respective discrete computation implementing the data flow model; and wherein a first PE of the second subset of PEs is configured to perform its respective discrete computation on receipt of a ready to receive output signal from one or more destination PEs; wherein the one or more destination PEs are configured to perform a computation on the output of the first PE according to the data flow model.