Reconfigurable PIM Architecture for ML Energy Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computer architectures, such as the von-Neumann architecture, are inadequate for supporting machine learning and artificial intelligence applications due to their inefficiencies in energy consumption, latency, and memory usage, and existing custom accelerators and FPGAs lack flexibility and energy efficiency.
Innovation Solution
A heterogeneous multi-functional reconfigurable processing-in-memory (PIM) architecture that uses dynamic random-access memory (DRAM) based multifunctional lookup table (LUT) cores to perform compute-intensive operations like multiply and accumulate (MAC) and activation functions, reducing the number of LUTs required and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional von-Neumann architecture is used, then hardware simplicity is maintained, but energy efficiency and processing performance deteriorate due to physical separation of memory and processing units
Solution Approach 1:
The patent merges memory and processing units into a unified processing-in-memory (PIM) architecture, where lookup table cores are directly integrated within memory banks. This eliminates the physical separation between memory and processing, allowing data to be processed in-place without transfer overhead, thereby improving energy efficiency while accepting increased architectural complexity
Solution Approach 2:
The patent implements multifunctional lookup table cores that can perform various operations including MAC operations, activation functions, and other computing tasks. These reconfigurable cores provide universal functionality within the memory structure, enabling the system to handle diverse workloads efficiently
2Adaptability or versatility
If custom-designed ASIC accelerators are used, then energy efficiency and processing performance improve, but flexibility and adaptability deteriorate due to fixed functionality
Solution Approach 1:
The patent implements dynamically reconfigurable lookup table cores that can be programmed to perform different functions based on workload requirements. This dynamic adaptability allows the same hardware structure to be optimized for different operations (MAC, activation functions, etc.), providing flexibility comparable to FPGAs while maintaining energy efficiency through in-memory processing
Solution Approach 2:
The multifunctional LUT cores can be configured to perform various computing operations including multiply-accumulate operations, activation functions (sigmoid, ReLU, tanh), and other neural network operations. This universal functionality eliminates the need for separate dedicated hardware for each operation type
3Use of energy by moving object
If FPGAs are used, then flexibility and reprogrammability improve, but energy efficiency and device complexity worsen due to reconfiguration overhead
Solution Approach 1:
The patent combines the processing functionality directly within the memory structure, eliminating the need for separate reconfigurable logic layers as in FPGAs. The lookup table cores are integrated into the memory banks themselves, reducing the overall device complexity and eliminating reconfiguration overhead while maintaining energy efficiency
4Productivity
If logic-gate-based arithmetic is used for MAC operations, then computational flexibility is maintained, but processing performance and energy efficiency deteriorate due to computational overhead
Solution Approach 1:
The patent replaces traditional logic-gate-based arithmetic circuits with lookup table-based computation. Instead of using sequential logic gates to perform multiply-accumulate operations, the system uses pre-computed lookup tables stored in memory, which can be retrieved and processed more efficiently, improving both performance and energy efficiency
Data Source
AI summary
A processing-in-memory (PIM) system includes a plurality of PIM clusters interconnected by a router in one or more dynamic random-access memory (DRAM) banks. The PIM clusters include one or more multiply and accumulate (MAC) processing elements including a plurality of MAC lookup table cores operatively configured to perform arithmetic logic, and one or more special function (SF) processing elements, wherein the one or more SF processing elements including a plurality of SF lookup table cores operatively configured to perform one or more machine learning activation functions. The MAC lookup tables include a first arithmetic logic unit (ALU) lookup table core type operatively configured to perform addition or multiplication operations, and a second ALU lookup table core type operatively configured to simultaneously perform both addition and multiplication operations. The MAC lookup table cores and SF lookup table cores are configured to perform convolutional neural network acceleration.