Reconfigurable Pipeline Processor Architecture for Signal Processing
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Solution Overview
Problem
Current processor architectures for digital signal processing in devices struggle with accommodating the convergence of diverse real-time signal processing needs, leading to complex, inflexible, and costly systems that are difficult to scale and adapt to new features and standards.
Innovation Solution
A programmable core with a reconfigurable pipeline that combines microprocessor-based technology and switch fabric technology, allowing for dynamic and flexible configuration of processor components to suit specific applications, enabling efficient parallel processing and reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple dedicated processor cores (DSP, GPP, ASIC) are combined in a single SoC to meet diverse signal processing needs, then processing capability and versatility are improved, but device complexity, die area, and power consumption increase significantly
Solution Approach 1:
The patent implements a universal processor core that can dynamically reconfigure its pipeline architecture to perform multiple signal processing functions. Instead of using separate dedicated cores for different processing tasks, a single core is designed with reconfigurable pipeline stages that can be dynamically adjusted to handle various algorithms (FFT, filtering, encoding, etc.), thereby reducing the number of cores needed while maintaining versatility
Solution Approach 2:
The processor employs dynamic reconfiguration of pipeline stages through control signals that modify the behavior and connectivity of pipeline components during runtime. This allows the same hardware structure to adapt to different processing requirements, transforming from a static architecture to a dynamic one that can optimize its configuration based on the current processing task
2Productivity
If dedicated hardware blocks are added for specific features to optimize processing performance, then processing speed is improved, but die area and power consumption increase due to hardware that is not simultaneously exercised
Solution Approach 1:
The patent designs universal processing units with reconfigurable pipeline stages that can be dynamically allocated to different processing functions. Instead of having dedicated hardware blocks for each feature, the same hardware resources are shared across multiple functions through time-multiplexed reconfiguration, reducing the total die area required while maintaining high processing speeds for each specific function when needed
Solution Approach 2:
The reconfiguration of pipeline stages occurs periodically or on-demand based on processing requirements, allowing the hardware to switch between different functional configurations. This periodic reconfiguration enables the same hardware to serve multiple purposes sequentially, optimizing processing speed for each task while minimizing the permanent hardware footprint
3Productivity
If pipeline architecture is used to increase execution speed, then throughput is improved, but the architecture loses flexibility when calculation order differs from functional block alignment
Solution Approach 1:
The patent implements dynamic reconfiguration of pipeline stage connections and data flow paths based on the specific algorithm being executed. Control logic dynamically adjusts the pipeline configuration to match the required calculation order, allowing the pipeline to maintain high throughput while adapting to different algorithmic requirements rather than being constrained by a fixed functional block arrangement
4Adaptability or versatility
If conventional DSP and GPP techniques are used to meet emerging signal processing needs, then programmability is maintained, but real-time performance and control processing capability are insufficient
Solution Approach 1:
The patent creates a universal processor that combines the programmability of GPP with the real-time performance characteristics of DSP. The reconfigurable pipeline architecture allows the processor to be programmed for different applications while maintaining optimized execution paths for real-time signal processing tasks, bridging the gap between the flexibility of software-defined processing and the performance of hardware-optimized processing
Data Source
AI summary
A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software for each specific application by communication through a switch fabric in a dynamic, parallel and flexible fashion to achieve a reconfigurable pipeline, wherein the length of the pipeline stages and the order of the stages varies from time to time and from application to application, admirably handling the explosion of varieties of diverse signal processing needs in single devices such as handsets, set-top boxes and the like with unprecedented performance, cost and power savings, and with full application flexibility.