Reconfigurable Pipelined Core for Algorithmic Processing Overhead
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Solution Overview
Problem
Conventional processors are not reconfigurable, leading to significant overhead in processing algorithmic functions, which limits their performance and efficiency, especially in handling mathematical operations and logical decisions, and existing reconfigurable systems like FPGAs are difficult to program and configure for practical applications.
Innovation Solution
A pipelined, parallel processor on a chip with a reconfigurable field programmable gate array, programmed by an algorithmic matching pipelined compiler, which precompiles source code for standard processors to operate as reusable algorithmic pipelined cores, reducing overhead and enhancing performance by allowing parallel processing without further intervention from the central processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional processors are used with general purpose architecture, then they can handle various algorithms, but they incur significant overhead in processing algorithmic functions
Solution Approach 1:
The processor architecture dynamically reconfigures its hardware structure based on the algorithm being executed. The field programmable gate array (FPGA) portion can be reconfigured to implement specific algorithmic functions, transforming the static general-purpose processor into a dynamic system that adapts its hardware architecture to match the computational requirements of the current task, thereby eliminating interpretation overhead.
Solution Approach 2:
The system changes the operational parameters of the processor by switching between different hardware configurations. The FPGA can be reprogrammed with different logic circuits and data paths depending on the algorithm, effectively changing the physical parameters of the processing unit to optimize for specific computational patterns while maintaining general applicability.
2Loss of time
If reconfigurable systems like FPGAs are used to reduce overhead, then processing speed improves, but they become difficult to program and configure
Solution Approach 1:
The patent introduces an intermediate software layer that acts as a mediator between the high-level programming language and the reconfigurable hardware. This intermediary translates standard programming constructs into FPGA configuration instructions, shielding the user from the complexity of hardware configuration while enabling the benefits of reconfigurable processing.
Solution Approach 2:
The system provides a universal programming interface that works across different algorithms and applications. The reconfigurable processor can be programmed using standard high-level languages for diverse computational tasks, making the complex FPGA technology as easy to use as conventional processors while maintaining the ability to optimize specific algorithms.
3Device complexity
If conventional processors execute instructions sequentially with program execution control, then they maintain simplicity in architecture, but performance is significantly limited
Solution Approach 1:
The processor is segmented into distinct functional units: a control processor for managing program execution and an FPGA array for parallel algorithmic processing. This segmentation allows the simple control processor to handle high-level instruction sequencing while the FPGA handles computationally intensive operations in parallel, dramatically improving productivity without complicating the overall architecture.
Solution Approach 2:
The system transitions from single-dimensional sequential execution to multi-dimensional parallel processing. While the control processor operates sequentially in one dimension, the FPGA array processes multiple operations simultaneously in parallel dimensions, effectively adding a temporal and spatial dimension to instruction execution that dramatically increases throughput while maintaining architectural simplicity.
Data Source
AI summary
An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.