Reconfigurable Pipelined Processors With Low Execution Overhead
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Solution Overview
Problem
Conventional processors are not reconfigurable, leading to significant overhead in processing algorithmic functions, limiting their performance in specific applications and requiring substantial intervention from central or peripheral processors for data and result handling.
Innovation Solution
A pipelined, parallel processor architecture with reconfigurable field programmable gates, configured by an algorithmic matching pipelined compiler, which precompiles source code to operate as pipelined, parallel processors, reducing overhead and enabling independent execution of complex mathematical and logical algorithms without further intervention from conventional processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional processors use general purpose architecture with program execution control, then they can execute various programs, but processing overhead increases significantly
Solution Approach 1:
The processor architecture dynamically reconfigures its hardware structure based on the algorithm being executed. Field programmable gates can be programmed to create different data flow paths and processing units, transforming the static general-purpose architecture into a dynamic specialized architecture that eliminates program execution overhead for specific algorithms while maintaining versatility across different applications.
Solution Approach 2:
The invention changes the operational parameters of the processor by allowing reconfiguration of field programmable gates. This enables the same hardware to operate in different modes (general-purpose vs. algorithm-optimized) by changing the programming of the gates, thereby reducing overhead for specific algorithms while maintaining general applicability.
2Ease of operation
If conventional processors use centralized control for data and result handling, then they can manage complex algorithms, but performance is limited by intervention overhead
Solution Approach 1:
The processor is segmented into independent processing units with dedicated data paths. Each unit can handle specific aspects of algorithm execution autonomously, breaking the centralized control bottleneck. Data and results are handled by distributed units rather than requiring constant central intervention, thereby improving productivity while maintaining ease of operation through modular design.
Solution Approach 2:
Processing units are designed to be self-sufficient, with local control logic that enables them to manage their own data flow and operations without requiring constant intervention from central control. This self-service capability reduces the overhead of centralized management while maintaining the ability to execute complex algorithms through coordinated operation of autonomous units.
3Speed
If field programmable gates are used for reconfiguration, then processing speed increases, but verification of timing constraints becomes difficult
Solution Approach 1:
The system performs preliminary analysis and optimization of the algorithm before generating the field programmable gate configuration. The compiler analyzes timing constraints and data flow requirements in advance, pre-calculating optimal paths and configurations that inherently satisfy timing requirements. This preliminary action eliminates the need for difficult post-configuration timing verification while maintaining high processing speed.
Solution Approach 2:
The invention incorporates feedback mechanisms where the compiler and configuration system use timing analysis results to iteratively optimize the field programmable gate configuration. Timing constraints are fed back into the configuration process, allowing automatic adjustment of data paths and resource allocation to meet timing requirements, thereby reducing verification complexity while maintaining high speed performance.
Data Source
AI summary
An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a high throughput processor system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.