Reconfigurable PLL with LC Oscillator for Wide Frequency Control
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Solution Overview
Problem
Existing phase-locked loops (PLLs) are not reconfigurable, making them difficult to integrate with configurable circuitry like FPGAs and requiring fixed IC layouts, limiting their use across various frequency ranges, jitter levels, and environmental conditions.
Innovation Solution
A reconfigurable digital phase-locked loop that generates a frequency reference or delay with phase detection, allowing for configuration of parameters such as frequency, bandwidth, jitter level, and power consumption, and can be integrated into any IC design with a variable IC layout, using a circuitry netlist and standard cells of any silicon fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed IC layout PLL design is used, then the PLL can be provided as a black box design with predetermined layout, but the PLL cannot be readily inserted into any selected IC design without accommodating the fixed floorplan and significantly affecting the overall IC area and timing
Solution Approach 1:
The PLL design transitions from a static, fixed floorplan to a dynamic, reconfigurable layout that can adapt to different IC design requirements. The circuit elements are arranged in a modular fashion that allows the floorplan to be dynamically adjusted during the design process to fit various IC areas and timing constraints without requiring significant redesign.
Solution Approach 2:
The PLL is designed with universal interfaces and a flexible architecture that enables it to function as a multi-functional component. The same PLL core can be instantiated with different configurations (dividers, multipliers, phase detectors) to serve various frequency synthesis applications across different IC designs, eliminating the need for application-specific custom designs.
2Device complexity
If a non-reconfigurable PLL is used, then the PLL circuit design can be simplified, but the PLL cannot be configured for a wide frequency range, desired jitter level, or power usage while maintaining accuracy
Solution Approach 1:
The PLL is divided into independent, modular segments including the phase detector, charge pump, voltage-controlled oscillator, frequency dividers, and feedback paths. Each segment can be independently configured or selected based on the desired frequency range and performance requirements, allowing the system to maintain accuracy across wide frequency ranges without proportionally increasing overall complexity.
Solution Approach 2:
The PLL incorporates configurable parameters such as division ratios, multiplication factors, and feedback path selections that can be changed through control signals or programming. This allows the same physical circuit to be reconfigured for different frequency ranges, jitter levels, and power consumption modes without hardware changes, maintaining design simplicity while achieving high adaptability.
3Stability of the object's composition
If a fixed frequency PLL is used, then the PLL can maintain stable operation, but the PLL cannot be reconfigured for fractional frequency generation or different frequency ranges
Solution Approach 1:
The PLL employs feedback mechanisms through programmable frequency dividers and phase detectors that continuously monitor the output frequency and adjust control signals to maintain phase lock. This feedback system enables stable operation across different frequency ranges and supports fractional frequency generation by dynamically adjusting division ratios while maintaining locked phase relationship between reference and output signals.
Data Source
AI summary
A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and delay generator is configured as the delay line circuit.