Reconfigurable Processor Code Compression for Low-Memory Configuration
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Solution Overview
Problem
Coarse-grained reconfigurable processors face challenges with excessive memory occupation and power consumption due to long code lengths required for processing functions, which are not adequately addressed by existing code compression methods.
Innovation Solution
A coarse-grained reconfigurable processor design that includes a configuration memory with a header storing compression mode indicators and compressed codes, and a decompressor that specifies corresponding codes from a body storing uncompressed codes, allowing reconfiguration of processing elements' data paths based on these indicators and codes, employing kernel-specific, global, and unit dictionaries for efficient compression and decompression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If code compression is not performed, then code length is sufficient for processing functions, but on-chip memory area and power consumption are excessively occupied
Solution Approach 1:
The code is divided into two segments: frequently used codes are stored in a small dictionary in the header for quick access, while less frequent codes are stored in the body. This segmentation allows the system to use short codes for common operations (maintaining high processing speed) while compressing the overall code length stored in configuration memory, thereby reducing power consumption and memory area without sacrificing processing productivity.
2Quantity of substance
If dictionary size is increased to improve compression efficiency, then more codes can be stored, but compression efficiency decreases and overflow processing becomes complex
Solution Approach 1:
The patent introduces a two-dimensional code structure with a header dimension (containing dictionary and compression codes) and a body dimension (containing uncompressed codes). This dimensional organization allows the system to handle a large number of codes efficiently: the header provides quick access to common codes while the body stores additional codes, eliminating the need for complex overflow processing that would occur with a single large dictionary.
3Quantity of substance
If statistical compression scheme is used to improve compression rate for frequently used codes, then compression rate increases, but parallel decompression becomes difficult
Solution Approach 1:
The patent introduces a dictionary as an intermediary layer between the compressed code and the actual function codes. The header contains a dictionary that maps compressed codes to their corresponding full codes. This intermediary structure enables both high compression rates (by using short codes for frequent operations) and efficient parallel decompression (by allowing simultaneous dictionary lookups for multiple compressed codes without complex decoding dependencies).
Data Source
AI summary
A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.