Dynamically Reconfigurable Processor Compiler Mapping
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Solution Overview
Problem
Existing computational systems based on Turing and von Neumann architectures are inefficient in utilizing high-level programming languages, as they require sequential execution of instructions and lack dynamic reconfiguration capabilities, limiting their ability to efficiently map software-coded information onto reconfigurable logic circuits.
Innovation Solution
A dynamically reconfigurable processor system that uses a compiler to automatically convert high-level language instructions into reconfigurable circuit configurations, enabling the execution of complex instructions and improving the mapping of software constructs onto reconfigurable logic circuits without the need for a fixed instruction set.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed instruction set architecture is used, then the system is simple to implement, but it cannot efficiently execute high-level language instructions or be dynamically reconfigured
Solution Approach 1:
The processor architecture transitions from a fixed instruction set to a dynamically reconfigurable structure where the instruction set can be modified at runtime. The control unit can load different microcode sequences to implement different high-level language instructions, allowing the same hardware to adapt to various programming languages and computational tasks without physical reconfiguration.
Solution Approach 2:
The processor is designed with a universal control unit that can execute multiple types of instructions by loading appropriate microcode. This single control unit serves multiple functions by interpreting different high-level language constructs (loops, conditionals, arithmetic operations) through a common architecture, eliminating the need for separate dedicated circuits for each instruction type.
2Productivity
If sequential execution of instructions is used, then the control logic is simple, but the execution speed and efficiency are limited
Solution Approach 1:
The system performs preliminary compilation of high-level language code into intermediate representation or microcode sequences before execution. This pre-processing step prepares the instruction stream in advance, allowing the control unit to execute pre-computed instruction sequences more efficiently without requiring complex real-time decision-making logic during runtime.
Solution Approach 2:
The instruction execution process is divided into distinct phases: fetching microcode from memory, decoding the intermediate representation, executing the control logic, and updating state. This segmentation allows each phase to be optimized independently and enables parallel processing of different instruction components, improving overall execution throughput.
3Adaptability or versatility
If software-coded information is directly mapped to reconfigurable logic circuits, then flexibility is improved, but the mapping complexity and compilation difficulty increase
Solution Approach 1:
An intermediate representation layer is introduced between the high-level source code and the reconfigurable logic circuit implementation. This intermediate form serves as a mediator that captures the essential computational structure without the full complexity of the original high-level language, making it easier to translate into hardware logic while preserving the desired flexibility and functionality.
Data Source
AI summary
A method and system are provided for deriving a resultant compiled software code with increased compatibility for placement and routing of a dynamically reconfigurable processor.