Reconfigurable Processor Architecture for Compute-Memory Balance

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Solution Overview

Problem

Conventional processing units, such as CPUs and GPUs, fail to provide a balanced combination of high computational intensity, high memory capacity, and high communication bandwidth, limiting their effectiveness in applications requiring flexible and efficient data processing.

Innovation Solution

A configurable processing architecture comprising a core processing element and multiple assist processing elements, connected via networks, with configurable compute logic and memory resources, allowing dynamic reconfiguration through bitstreams for optimized execution of various applications, including neural networks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional CPUs are used, then high memory capacity and high communication bandwidth are provided, but computational intensity is relatively lower

Engineering Contradiction:
Improvecomputational intensityVSAvoidflexibility for different application types
Core Design Contradiction:
PowerVSAdaptability or versatility

Solution Approach 1:

The processing architecture employs dynamic reconfiguration capabilities where the system can switch between different operational modes (CPU-like, GPU-like, or hybrid modes) based on the specific computational requirements of the workload. This allows the same hardware to adapt its computational intensity and memory bandwidth characteristics dynamically, resolving the contradiction between fixed architectural strengths and varying application needs

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements a universal processing platform that can perform both traditional CPU functions (sequential processing, high memory bandwidth) and GPU functions (parallel processing, high computational intensity) within a single system. This multi-functionality eliminates the need for separate specialized processors while maintaining both memory capacity and computational intensity through configurable operational modes

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Power

If conventional GPUs are used, then higher computational intensity is provided, but memory capacity and communication bandwidth are relatively low

Engineering Contradiction:
Improvecomputational intensityVSAvoidmemory capacity
Core Design Contradiction:
PowerVSQuantity of substance

Solution Approach 1:

The architecture merges the computational processing units with high-capacity memory subsystems into an integrated structure. By combining GPU-like computational elements with CPU-like memory bandwidth capabilities in a unified system, the design achieves both high computational intensity and high memory capacity simultaneously, rather than treating them as separate trade-offs

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If specialized processing units are used for specific applications, then performance is optimized, but adaptability to other applications is reduced

Engineering Contradiction:
Improveperformance for specific applicationsVSAvoidflexibility for different applications
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system employs dynamic reconfiguration capabilities where the processing architecture can be programmatically adjusted to optimize performance for different application types. By loading different configuration parameters and operational modes, the same hardware platform achieves application-specific performance optimization while maintaining the ability to adapt to new workloads, resolving the contradiction between specialization and versatility

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12517862B2Configurable processing architecture
Publication Date: 2026.01.06 ALIBABA GROUP HOLDING LTD
  • US12517862B2 patent drawing
  • US12517862B2 patent drawing
  • US12517862B2 patent drawing

AI summary

A configurable processing unit including a core processing element and a plurality of assist processing elements can be coupled together by one or more networks. The core processing element can include a large processing logic, large non-volatile memory, input/output interfaces and multiple memory channels. The plurality of assist processing elements can each include smaller processing logic, smaller non-volatile memory and multiple memory channels. One or more bitstreams can be utilized to configure and reconfigure computation resources of the core processing element and memory management of the plurality of assist processing elements.