Reconfigurable Processor Core Sharing Coarse Grained Array
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Solution Overview
Problem
Conventional processors face limitations in flexibility and performance enhancement post-fabrication, as they either require hardware modifications or suffer from reduced speed when adding new functions through software, and multi-core architectures are needed to overcome single-core performance limitations.
Innovation Solution
A reconfigurable processor core architecture utilizing a Very Long Instruction Word (VLIW) processor and Coarse Grained Array (CGA) that allows for parallel instruction execution and sharing of functional units between processor cores, enabling efficient execution of multiple instruction sets and optimizing performance with minimal additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware modifications are made to add new functions after fabrication, then new functions can be added, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements dynamic reconfigurability by introducing a configuration memory and control logic that allows the processor architecture to change its functional units and data paths after fabrication. The functional units can be dynamically reconfigured to perform different operations (e.g., ADD, SUB, MUL, DIV) based on configuration bits stored in memory, enabling post-fabrication function customization without hardware modifications.
Solution Approach 2:
The patent creates universal functional units that can perform multiple operations. The arithmetic logic units are designed to execute various arithmetic and logical operations by changing their configuration state, allowing a single hardware structure to serve multiple purposes. This multi-functionality eliminates the need for separate dedicated hardware for each function.
2Adaptability or versatility
If software is used to add new functions after fabrication, then flexibility is improved, but execution speed decreases
Solution Approach 1:
The patent replaces software-based function implementation with hardware-based reconfigurable logic. Instead of executing software instructions in a general-purpose processor, the functional units are physically reconfigured through configuration memory to perform specific operations in hardware, achieving both flexibility and high-speed execution comparable to dedicated hardware.
Solution Approach 2:
The patent changes the operational parameters of functional units by modifying configuration bits in memory. These parameter changes control the behavior of arithmetic logic units, data path widths, and operation types, allowing the same hardware structure to adapt to different computational requirements while maintaining high-speed performance.
3Productivity
If multiple processor cores are added to improve performance, then parallelism increases, but hardware area increases
Solution Approach 1:
The patent merges multiple processor cores into a unified reconfigurable architecture. Instead of implementing separate independent cores, the system uses a shared array of reconfigurable functional units that can be dynamically allocated to different cores or tasks. This consolidation achieves multi-core parallelism while reducing the total hardware area compared to traditional multi-core designs.
Solution Approach 2:
The patent implements dynamic resource allocation where the reconfigurable functional units can be assigned to different processor cores or computational tasks based on runtime requirements. This dynamic sharing allows the same hardware resources to serve multiple cores, achieving parallelism without proportionally increasing hardware area.
4Speed
If dedicated hardware is used for specific functions, then execution speed is high, but adaptability after fabrication is lost
Solution Approach 1:
The patent makes dedicated hardware dynamic and reconfigurable. The functional units that would traditionally be fixed for specific operations are instead controlled by configuration memory, allowing them to be reprogrammed for different functions. This maintains high-speed hardware execution while adding post-fabrication adaptability through configurable logic control.
Data Source
AI summary
A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.