Reconfigurable Processor Core with Dynamic Execution Slices
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Solution Overview
Problem
Existing processor cores have fixed resource types and pipelines, leading to inefficient use of resources, with some resources remaining unused except during rare occasions, which can hinder performance and waste die area.
Innovation Solution
A processor core with reconfigurable architecture that includes multiple parallel instruction execution slices, dispatch queues, cache slices, and load-store slices, allowing for dynamic allocation of resources based on thread mode control signals to optimize resource usage and support single-threaded, multi-threaded, and super-slice configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed resource types and pipelines are provided in processor design, then resource allocation is simplified, but resource utilization efficiency deteriorates with resources remaining unused except during rare occasions
Solution Approach 1:
The processor implements dynamic resource allocation through thread mode control signals that can reconfigure execution slices between single-threaded and multi-threaded modes. Execution slices can be dynamically assigned to different threads based on workload requirements, allowing resources to adapt their function and improve utilization efficiency without increasing allocation complexity
Solution Approach 2:
Execution slices are designed to perform multiple functions by supporting both single-threaded and multi-threaded operation modes. The same physical resources can serve different thread configurations, enabling one resource type to fulfill multiple roles and reduce idle time across different operational scenarios
2Ease of manufacture
If specific execution resources are fixed in processor core design, then design simplicity is improved, but performance is hindered due to absent particular types of execution resources in certain core types
Solution Approach 1:
The processor divides execution resources into multiple independent execution slices that can be individually configured and activated. This segmentation allows different core types to include or exclude specific slice configurations during manufacturing, maintaining design simplicity while enabling performance optimization for different application scenarios
Solution Approach 2:
The processor allows configuration of execution slice parameters through control signals that enable or disable specific slice functionalities. This parameter-based configuration lets manufacturers produce different core variants by setting appropriate default parameters without changing the fundamental hardware design
3Reliability
If resources within processor core are allocated for rare occasions, then resource availability for specific functions is improved, but die area is wasted that might otherwise be used to increase processor core performance
Solution Approach 1:
Multiple execution slices are merged into a unified resource pool that can be dynamically allocated to different threads. Resources that would traditionally be dedicated to specific rare-function handling are merged with general-purpose execution resources, eliminating redundant allocations and reducing die area while maintaining availability through dynamic sharing
Data Source
AI summary
A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.