Reconfigurable Processor Element Network for High-Speed Processing
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Solution Overview
Problem
Reconfigurable integrated circuit devices face inefficiencies in processing due to fixed arithmetic unit combinations leading to useless clock cycles and reduced flexibility, limiting high-speed processing when switching between different calculation states.
Innovation Solution
A reconfigurable integrated circuit device with a processor element comprising multiple arithmetic units connected in parallel, where the intra-processor and inter-processor networks can be dynamically reconfigured based on configuration data to optimize connections and reduce latency, allowing for high flexibility and efficient utilization without useless clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If arithmetic units are connected in series in a fixed combination, then the processing speed is improved when the specific calculation state is used, but the flexibility and utilization efficiency deteriorate when switching to different calculation states
Solution Approach 1:
The patent applies dynamics by making the connection structure between arithmetic units changeable rather than fixed. The intra-processor network allows dynamic reconfiguration of connections between arithmetic units based on configuration data, enabling the system to adapt its internal structure to match different calculation states and eliminate useless clock cycles
Solution Approach 2:
The patent implements universality by designing arithmetic units that can be connected in multiple configurations through the reconfigurable intra-processor network. Each arithmetic unit can serve different functions depending on how it is connected within the network, allowing the same hardware components to be optimized for different calculation states
2Adaptability or versatility
If arithmetic units are reconfigured to a completely different combination, then the flexibility is improved, but the utilization efficiency deteriorates and useless clock cycles occur
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple arithmetic units within each processor element and establishing the intra-processor network structure in advance. This allows the system to quickly switch between different calculation states by activating pre-established connection patterns, avoiding the need to create new configurations from scratch and thereby eliminating useless clock cycles
Solution Approach 2:
The patent ensures continuity of useful action by designing the intra-processor network to maintain continuous data flow between arithmetic units during state transitions. The reconfigurable connections allow the system to transition smoothly between different calculation states without interrupting the processing pipeline, ensuring that arithmetic units remain productive across state changes
Data Source
AI summary
A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.