Multistage Workflow for Reconfigurable Processor Instruction Set Generation
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Solution Overview
Problem
The development of instruction sets for reconfigurable processors, such as FPGAs, is challenging due to the requirement for specialized hardware-level skills and knowledge, limiting the ability to create optimized processor configurations efficiently.
Innovation Solution
A multistage workflow that uses description files to parse program code into custom instructions and capability descriptions, allowing for the generation of reconfigurable processor loadable instruction sets without specialized hardware skills, using standard programming languages and pragmas, and facilitating rapid performance analysis and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional hardware-level development methods are used for reconfigurable processors, then development precision and control are improved, but development complexity and skill requirements increase
Solution Approach 1:
The patent introduces a compiler as an intermediary tool that translates high-level programming languages into hardware configuration code for reconfigurable processors. This mediator allows developers to work with familiar software tools and languages while the compiler handles the complex hardware-level transformations, thus maintaining development precision while reducing the perceived complexity for end users.
Solution Approach 2:
The patent replaces manual hardware-level configuration methods with an automated compiler-based system. Instead of requiring developers to directly manipulate hardware description languages and configuration files, the system uses a compiler to automatically generate the necessary hardware configuration from high-level source code, substituting mechanical hardware manipulation with software-based automation.
2Manufacturing precision
If specialized hardware skills are required for development, then development quality is improved, but accessibility and ease of operation deteriorate
Solution Approach 1:
The patent creates a universal development environment where a single compiler toolchain can handle multiple tasks: compiling high-level source code, generating hardware configuration, optimizing instruction sets, and configuring reconfigurable processors. This multi-functional system allows developers with standard programming skills to perform tasks that traditionally required specialized hardware expertise, thus improving accessibility while maintaining quality through the compiler's optimized code generation.
3Manufacturing precision
If manual optimization methods are used, then optimization precision is improved, but development time and productivity worsen
Solution Approach 1:
The patent implements a self-optimizing compiler system that automatically analyzes source code, identifies optimization opportunities, and generates optimized hardware configurations without requiring manual intervention. The compiler performs self-service optimization by examining the high-level source code, applying optimization algorithms, and directly generating optimized instruction sets and hardware configurations, thus achieving high optimization precision while maintaining rapid development throughput.
Solution Approach 2:
The patent performs optimization actions in advance during the compilation process, before the hardware is actually configured or executed. The compiler pre-analyzes the source code, pre-optimizes the instruction sets, and pre-generates the hardware configuration, so that when the reconfigurable processor is deployed, the optimization work is already complete. This preliminary optimization action eliminates the need for time-consuming manual tuning while maintaining high optimization quality.
Data Source
AI summary
Systems and methods which implement workflows for providing reconfigurable processor core algorithms operable with associated capabilities using description files, thereby facilitating the development and generation of instruction sets for use with reconfigurable processors, are shown. Embodiments implement a multistage workflow in which program code is parsed into custom instructions and corresponding capability descriptions for generating reconfigurable processor loadable instruction sets. The multistage workflow of embodiments includes a hybrid threading complier operable to compile input program code into custom instructions using a hardware timing agnostic approach. A timing manager of the multistage workflow of embodiments utilizes capabilities information provided in association with the custom instructions generated by the hybrid threading complier to impose hardware timing on the custom instructions. A framework generator and hardware description language complier are also included in the multistage workflow of embodiments.