Reconfigurable Processor Allocation by Link Bandwidth and Latency

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Solution Overview

Problem

Deep neural networks are becoming increasingly complex and deep, leading to higher computation times and prediction latencies, with inter-accelerator communication requirements constraining multi-accelerator application efficiency, particularly in data center environments.

Innovation Solution

A data processing system with a pool of reconfigurable dataflow resources and runtime logic that allocates reconfigurable processors and links based on link bandwidths and latencies to optimize communication and execution of applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If multiple accelerators are used to process deep neural networks, then computation power increases, but inter-accelerator communication latency increases

Engineering Contradiction:
Improvecomputation powerVSAvoidcommunication latency
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The system segments the deep neural network processing workload across multiple accelerators, with each accelerator handling specific layers or operations. This segmentation enables parallel processing while the runtime logic optimizes data distribution to minimize communication overhead between segmented accelerator units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The runtime logic acts as an intermediary that manages data flow and communication between multiple accelerators. It optimizes inter-accelerator communication by selecting optimal data paths, buffering strategies, and synchronization mechanisms to reduce communication latency while maintaining high computation power.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If reconfigurable processors are allocated dynamically, then resource utilization improves, but allocation complexity increases

Engineering Contradiction:
Improveresource utilizationVSAvoidallocation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements dynamic reconfiguration of processors where the runtime logic can allocate and reconfigure processing resources on-the-fly based on workload requirements. This dynamic approach improves resource utilization by adapting to changing computational demands while the automated runtime logic manages the complexity of allocation decisions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The runtime logic incorporates feedback mechanisms that monitor processor utilization, workload characteristics, and performance metrics to make intelligent allocation decisions. This feedback-driven approach optimizes resource utilization while managing allocation complexity through automated decision-making based on real-time system state.

Inventive Principle:
Principle #23Feedback

3Speed

If link bandwidth is increased for accelerator communication, then data transfer speed improves, but system cost increases

Engineering Contradiction:
Improvedata transfer speedVSAvoidsystem cost
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The system changes the parameter of link bandwidth dynamically based on communication requirements. The runtime logic analyzes data transfer patterns and allocates appropriate bandwidth levels, using high bandwidth only when necessary and lower bandwidth for routine communications, thereby improving data transfer speed where needed while controlling system cost.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12413530B2Data processing system with link-based resource allocation for reconfigurable processors
Publication Date: 2025.09.09 SAMBANOVA SYSTEMS INC
  • US12413530B2 patent drawing
  • US12413530B2 patent drawing
  • US12413530B2 patent drawing

AI summary

The disclosed technology relates to link-based resource allocation for a pool of reconfigurable processors. Resource allocation is provided for reconfigurable processors based on link bandwidths and link latencies. Runtime logic receives target link bandwidth and target link latency and rated link bandwidth and rated link latency. In response, the runtime logic allocates configuration files for an application, reconfigurable processors, and links between the processors. The runtime logic executes the allocated configuration files using the allocated processors and the allocated links. In another embodiment, the pool of reconfigurable processors comprise a cluster of processing nodes connected through a network.