Reconfigurable Processor Memory Dependency Scheduling
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Solution Overview
Problem
Existing processing technologies face challenges in efficiently allocating instructions between multiple processing elements for parallel computation, particularly in handling loop computations with memory dependencies, which affects the speed and flexibility of digital signal processing.
Innovation Solution
A reconfigurable processor is designed with an extractor to analyze memory access instructions and a scheduler to determine memory dependencies, allowing for the allocation of instructions between processing elements based on calculated minimum iteration intervals, enabling parallel or serial processing to optimize loop computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are allocated between multiple processing elements for parallel processing, then processing speed is improved, but handling of memory dependencies becomes complex and accuracy may deteriorate
Solution Approach 1:
The system performs preliminary simulation of loop computations to generate execution traces before actual parallel processing. The scheduler uses these traces to pre-analyze memory dependencies and determine safe allocation strategies, ensuring computation accuracy is maintained while enabling parallel processing.
Solution Approach 2:
An execution trace acts as an intermediary between the loop computation instructions and the scheduler. The trace captures memory access patterns and dependencies, allowing the scheduler to make informed decisions about instruction allocation without directly analyzing the complex dependency structure of the original instructions.
2Productivity
If software pipelining is applied to reconfigurable arrays, then performance is improved, but proper handling of memory dependency instructions becomes difficult
Solution Approach 1:
The system uses execution traces obtained from simulation as feedback to the scheduler. The scheduler analyzes these traces to understand memory dependency patterns and adjusts instruction allocation accordingly, creating a closed-loop system that continuously optimizes performance while maintaining correctness.
Solution Approach 2:
The patent replaces manual or direct analysis of memory dependencies with an automated simulation-based approach. The simulator generates execution traces that automatically capture dependency information, substituting complex manual dependency analysis with automated trace-driven scheduling.
3Reliability
If iteration interval is increased from minimum iteration interval (MII), then memory dependency accuracy is improved, but processing efficiency may deteriorate
Solution Approach 1:
The scheduler analyzes only a portion of the execution trace corresponding to a single iteration window rather than the entire trace. This partial analysis is sufficient to determine memory dependencies for that iteration, avoiding excessive analysis while maintaining accuracy.
Solution Approach 2:
The system dynamically adjusts the iteration interval parameter based on analyzed memory dependencies. Rather than using a fixed interval, the scheduler modifies the interval parameter to balance between maintaining dependency accuracy and achieving processing efficiency for the specific loop being executed.
Data Source
AI summary
Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.