Reconfigurable Processor Memory Mapping for Loop Parallelism
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Solution Overview
Problem
Reconfigurable processors face inefficiencies in processing tasks with changed work contents due to fixed hardware functions, and software processing is slower, necessitating an optimization of hardware and software utility, particularly in digital signal processing.
Innovation Solution
A method and apparatus that analyze parallelism in program code loops to schedule function units and generate configuration data for efficient mapping in configuration memory, using classification letters and regular encoding to optimize memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all function units are activated in the configuration memory, then processing capability is improved, but configuration memory usage increases
Solution Approach 1:
The configuration memory is segmented into multiple rows, with each row corresponding to a specific cycle. Only the necessary function units for each cycle are activated and stored in the corresponding memory row, rather than storing all possible function units throughout. This segmentation allows the system to maintain high processing capability when needed while reducing overall memory usage by activating only necessary function units in each time segment.
2Quantity of substance
If configuration memory size is reduced, then memory efficiency is improved, but processing speed may decrease
Solution Approach 1:
The system performs preliminary analysis of parallelism in program code loops and pre-schedules function unit activations for each cycle before execution. By analyzing the loop structure and determining which function units will be needed in each cycle in advance, the system can efficiently map only the necessary function units to the configuration memory, reducing memory size while ensuring that processing speed is maintained through optimized pre-planning of the activation sequence.
Data Source
AI summary
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.