Reconfigurable Processor Hardware Message Management for Energy Efficiency
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Solution Overview
Problem
Existing reconfigurable arithmetic schemes in embedded terminals face challenges with low processing performance and high energy consumption, particularly in communication signal processing, image processing, and artificial intelligence tasks, where conventional CPU, GPU, and DSP schemes fall behind ASICs in performance, power, and area efficiency, and field-specific processors are inflexible and fragmented.
Innovation Solution
A reconfigurable processor system comprising a hardware message management module, memory management system, and arithmetic and logic unit, which reads, parses, and prioritizes hardware messages, storing them in memory and running them based on configured priorities, utilizing a unified hardware architecture with data flow and instruction flow driving, enabling efficient reconfiguration and improved PPA performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASIC scheme is used, then processing performance and energy efficiency are improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The patent implements a reconfigurable processor that can dynamically change its hardware architecture through configuration files. The processor includes reconfigurable computing units and interconnection structures that can be programmed to perform different algorithms, combining the high performance of ASIC with the flexibility of software-based systems. This dynamic reconfiguration capability allows the same physical hardware to adapt to different computational tasks while maintaining optimized performance for each specific algorithm.
2Productivity
If field-specific processors are used, then processing performance is improved, but device complexity and design fragmentation increase
Solution Approach 1:
The patent describes a universal reconfigurable processor architecture that can perform multiple types of computations through a single hardware platform. The processor includes configurable computing units, programmable interconnections, and a unified memory system that can be programmed to execute different algorithms for various applications such as signal processing, image processing, and AI workloads. This eliminates the need for multiple specialized processors while maintaining high performance for each specific task.
3Adaptability or versatility
If conventional CPU/GPU/DSP schemes are used, then flexibility is maintained, but processing performance and energy efficiency deteriorate
Solution Approach 1:
The patent replaces the sequential instruction-based execution model of conventional CPUs with a data-flow driven reconfigurable architecture. The processor uses configurable computing units that can be directly programmed with algorithm-specific logic through configuration files, eliminating the need for complex instruction decoding and control logic. This substitution of the traditional von Neumann execution model with a dedicated reconfigurable data processing architecture achieves both high performance and flexibility.
4Adaptability or versatility
If reconfigurable arithmetic schemes are used, then flexibility and PPA performance are improved, but processing performance and energy efficiency remain insufficient
Solution Approach 1:
The patent divides the processor into multiple independent reconfigurable computing units, each capable of performing specific computational functions. These computing units can be independently configured and operated, allowing parallel execution of different algorithmic operations. The segmentation enables fine-grained optimization of each computing unit for its specific function while maintaining overall system flexibility through programmable interconnections between the units.
Data Source
AI summary
Provided are a reconfigurable processor and a reconfigurable processor system, where the reconfigurable processor includes: a hardware message management module (110), a memory management system (120) and an arithmetic and logic unit (130). The memory management system (120) is connected to the hardware message management module (110) and the arithmetic and logic unit (130) respectively; the hardware message management module (110) is configured to read and parse at least one hardware message, to configure a priority of each of the at least one hardware message and store each of the at least one hardware message into a memory through the memory management system (120); and the arithmetic and logic unit (130) is configured to run the at least one hardware message according to the configured priority.