Reconfigurable Processor With Adaptive Pipeline Depths for Higher Throughput
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Solution Overview
Problem
Existing coarse-grained reconfigurable processors face challenges with low computing efficiency and clock frequency due to complex operations and differing pipelining depths of compute units, which hinder overall pipelining data processing.
Innovation Solution
A reconfigurable processor with adaptive pipeline depth control, utilizing a reconfiguration configuration unit to adjust the pipeline depth of computational arrays based on algorithm requirements, forming a data path pipeline structure with equal depths across stages, and employing FIFO groups for data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If compute units are designed with different pipelining depths to match computation complexity, then computation accuracy is improved, but overall pipelining data processing is hindered and computing efficiency deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the pipeline depth of computation modules based on the specific algorithm being executed. The reconfiguration configuration unit modifies pipeline depth parameters to match computation complexity requirements, allowing both high accuracy for complex operations and high efficiency for simpler operations through parameter optimization rather than fixed structural design
Solution Approach 2:
The patent implements dynamics by making the pipeline depth configurable and adaptable rather than fixed. The reconfiguration configuration unit enables the computation modules to dynamically adjust their pipeline depth according to different algorithm requirements, transforming a static architecture into a dynamic system that can optimize its structure for each computational task
2Adaptability or versatility
If reconfigurable array uses fully-functioning compute units with different pipelining depths, then computation versatility is improved, but data path pipeline structure formation becomes difficult and productivity deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the reconfigurable array into multiple computation modules, each capable of being independently configured with appropriate pipeline depth. This segmentation allows the system to maintain versatility through different module configurations while achieving high throughput by processing data through multiple stages in parallel
Solution Approach 2:
The patent implements universality by designing computation modules that can perform multiple functions with different pipeline depths. The same physical hardware can be reconfigured to serve as shallow or deep pipeline stages depending on the algorithm requirements, enabling both versatility and high productivity through a single multi-functional architecture
3Measurement precision
If reconfigurable array increases pipelining depth for complex operations, then computation precision is improved, but clock frequency decreases and computing efficiency deteriorates
Solution Approach 1:
The patent applies parameter changes by allowing the pipeline depth parameter to be dynamically adjusted based on computation requirements. For complex operations requiring high precision, the pipeline depth is increased while for simpler operations, the pipeline depth is reduced to maintain high clock frequency, thus optimizing the precision-speed tradeoff for each computational task
4Productivity
If reconfigurable array uses uniform pipelining depth across all compute units, then overall pipelining data processing is improved, but computation accuracy for complex operations deteriorates
Solution Approach 1:
The patent applies local quality by allowing different computation modules within the same reconfigurable array to have different pipeline depths optimized for their specific computational functions. This local optimization ensures that each module achieves the appropriate balance between speed and precision for its particular operation type, rather than imposing a uniform pipeline depth on all modules
Data Source
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AI summary
The present disclosure discloses a reconfigurable processor and a configuration method. The reconfigurable processor includes a reconfiguration configuration unit and a reconfigurable array. The reconfiguration configuration unit is configured to provide, according to an algorithm matched with a current application scenario, reconfiguration information used for reconfiguring a computation structure in the reconfigurable array. The reconfigurable array includes at least two stages of computational arrays, the reconfigurable array is configured to connect, according to the reconfiguration information provided by the reconfiguration configuration unit, adjacent two stages of the computational arrays to form a data path pipeline structure satisfying computation requirements of the algorithm. In the same stage of the computational array, pipeline depths of different computation modules connected to the data path pipeline structure are equal, such that the different computation modules connected to the data path pipeline structure synchronously output data. Thus, the reconfigurable processor can configure adaptive pipeline depths according to different algorithms, and on this basis, realizes overall pipelining of data processing operation of the reconfigurable array, thereby increasing the throughput of the reconfigurable processor.