Reconfigurable Processor Quiesce Control for CGRA Multitasking
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Solution Overview
Problem
Checkpointing, multitasking, and multiprogramming in distributed processing systems, such as coarse-grain reconfigurable architectures (CGRAs), present complex issues due to the lack of capability to interrupt execution for system management functions like pre-emptive multitasking and debugging, necessitating an efficient means to manage quiesce of processing units.
Innovation Solution
A processing system with quiesce logic and control circuits is introduced to manage quiesce operations in CGRAs, allowing for asynchronous processing units to synchronize at defined quiesce boundaries, using quiesce controllers, barrier tokens, and skew counters to coordinate producer and consumer operations, enabling efficient quiesce and resume of execution fragments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the runtime control program loads a configuration file and executes the machine to completion, then the processing operation can be performed efficiently, but there is no capability to interrupt the machine during execution for system management functions like multitasking and debugging
Solution Approach 1:
The patent implements preliminary action by pre-defining quiesce boundaries within the configuration data before execution begins. These boundaries mark specific points in the execution fragment where processing units can be safely quiesced. When an interrupt signal is received, the system checks if a quiesce boundary is available and transitions to quiesce mode at that predefined point, enabling multitasking and debugging without compromising processing efficiency during normal operation.
2Adaptability or versatility
If processing units are quiesced in a coarse-grain reconfigurable array, then system management functions like multitasking and debugging can be performed, but coordinating among distributed processing units becomes complex
Solution Approach 1:
The patent applies segmentation by dividing the array of processing units into distinct execution fragment resource groups (EFRGs), where each EFRG is allocated to implement a specific execution fragment. This segmentation allows independent quiesce control for each group through dedicated quiesce logic circuits, simplifying coordination compared to managing all processing units as a single distributed system. The configuration data explicitly defines which processing units belong to each EFRG and their quiesce boundaries.
Solution Approach 2:
The patent introduces quiesce logic circuits as intermediary components between the control signal and the processing units. These logic circuits receive quiesce control signals and translate them into coordinated actions for the processing units in the EFRG. The quiesce logic acts as a mediator that simplifies the coordination complexity by providing a standardized interface for quiescing distributed processing units, enabling multitasking and debugging functions.
3Reliability
If asynchronous processing units are synchronized on quiesce boundaries, then safe quiesce can be achieved, but additional synchronization logic is required
Solution Approach 1:
The patent implements preliminary action by pre-defining quiesce boundaries within the configuration data before execution begins. These boundaries mark specific points in the execution fragment where processing units can be safely quiesced. When an interrupt signal is received, the system checks if a quiesce boundary is available and transitions to quiesce mode at that predefined point, enabling multitasking and debugging without compromising processing efficiency during normal operation.
Data Source
AI summary
A computer system includes an array of reconfigurable processor blocks which execute fragments of a larger data processing operation. An array controller distributes a control signal to the reconfigurable processors in the array and receives control signals for the respective execution fragments. The control signal may include quiesce logic or other control methods to execute the effective execution fragments of the larger data processing operation when individual processors become available.