Dynamic Reconfigurable Processor Software-to-Hardware Mapping
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Solution Overview
Problem
Existing computational systems are inefficient in mapping software coded information onto dynamically reconfigurable logic circuits, as they rely on sequential instruction sets and hardware designs that do not allow for optimal parallel processing or efficient reconfiguration.
Innovation Solution
A method and system that automatically correlate software resources with dynamically reconfigurable processor components, using a compiler to convert high-level language instructions into reconfigurable circuit configurations, enabling efficient reconfiguration of logic circuits without human intervention and supporting parallel processing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential instruction sets are used in general-purpose computers, then the system maintains simplicity and compatibility with existing architectures, but processing efficiency deteriorates due to inability to perform optimal parallel processing
Solution Approach 1:
The patent implements dynamic reconfiguration of logic circuits where the processor architecture can change its structure at runtime based on the computational task. The system transitions from static sequential architecture to dynamic parallel architecture by reconfiguring logic elements, interconnects, and functional units to match the instruction being executed, thereby achieving high productivity without permanent complexity
Solution Approach 2:
The reconfigurable processor uses universal logic elements and interconnect structures that can be programmed to perform multiple different functions. The same physical hardware resources can be reconfigured to implement different arithmetic operations, logic functions, and data flow patterns, allowing one system to replace multiple specialized processors
2Adaptability or versatility
If fixed hardware designs are used, then manufacturing is simpler and more reliable, but adaptability deteriorates due to inability to efficiently reconfigure for different computing processes
Solution Approach 1:
The processor is divided into modular reconfigurable blocks including logic elements, interconnect matrices, and functional units. Each segment can be independently configured and reconfigured, allowing granular adaptation to different computational needs while keeping the overall system manageable through modular design
Solution Approach 2:
The patent introduces a compiler and configuration system as an intermediary layer between the high-level software and the reconfigurable hardware. This intermediary automatically translates software instructions into hardware configuration commands, shielding users from the complexity of direct hardware reconfiguration while enabling full adaptability
3Extent of automation
If software resources are manually mapped to processor components, then control precision is higher, but automation level deteriorates due to requiring human operator intervention
Solution Approach 1:
The system implements self-service through an automated compiler that performs the entire mapping process without human intervention. The compiler analyzes the software code, identifies computational patterns, and automatically generates the corresponding hardware configuration, allowing the system to configure itself based on the workload requirements
Solution Approach 2:
The patent incorporates feedback mechanisms where the compiler continuously monitors the execution performance and resource utilization, then adjusts the hardware configuration accordingly. This closed-loop control ensures that the automatic mapping achieves optimal precision by learning from actual runtime behavior and refining the software-to-hardware correspondence
4Productivity
If sequential execution methods are used, then implementation is simpler, but productivity deteriorates due to inability to execute complex instructions in parallel
Solution Approach 1:
The system employs periodic reconfiguration where the hardware architecture is dynamically adjusted in sync with the instruction stream. Between instruction executions, the logic circuits are reconfigured to match the upcoming operation, enabling each instruction to be executed in parallel with the reconfiguration preparation, thereby achieving high execution speed
Solution Approach 2:
The patent implements preliminary reconfiguration where the hardware is pre-configured for the next instruction before the current instruction completes execution. This lookahead approach allows the system to prepare parallel processing paths in advance, eliminating sequential bottlenecks and achieving pipelined execution of complex instructions
Data Source
AI summary
A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.