Reconfigurable Processor Time-Multiplexing for Hardware Utilization
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Solution Overview
Problem
Reconfigurable processors face underutilization of hardware resources due to idle periods when general-purpose hardware and reconfigurable hardware operate separately, leading to inefficiencies in executing applications.
Innovation Solution
A system that time-multiplexes programs on reconfigurable architectures by using a host and reconfigurable data processor with a configuration load/unload controller, allowing for dynamic configuration of configurable units and efficient execution of applications across both types of hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If general-purpose hardware and reconfigurable hardware operate separately, then each hardware type can be optimized for its specific function, but hardware resources become underutilized during idle periods
Solution Approach 1:
The patent combines general-purpose hardware and reconfigurable hardware into a unified system where the reconfigurable processor can dynamically switch between different configurations. The configuration load/unload controller manages the transition between hardware states, allowing the same physical resources to serve multiple functions sequentially, thereby eliminating idle periods and maximizing utilization.
Solution Approach 2:
The system implements dynamic reconfiguration where the reconfigurable processor can change its functional state during operation. The configuration controller enables the hardware to adapt its structure and function based on current computational needs, transforming static hardware resources into dynamic, multi-functional units that can respond to varying workload requirements.
2Speed
If reconfigurable hardware is used to execute applications, then execution speed and efficiency are improved, but configuration loading and unloading time increases overall processing time
Solution Approach 1:
The system performs configuration loading in advance before execution is needed. The configuration load/unload controller pre-loads configuration data into the reconfigurable processor during idle periods or before computation tasks are initiated, so that when execution begins, the hardware is already configured and ready to operate at full speed without waiting for configuration loading.
Solution Approach 2:
The patent maintains continuous useful action by overlapping configuration loading with execution of other tasks. While one configuration is being loaded, the processor can execute other computations or perform configuration unloading for previous tasks. This pipelining approach ensures that configuration time does not add to overall processing time, as configuration operations occur concurrently with execution operations.
Data Source
AI summary
An integrated circuit includes a plurality of configurable units, each configurable unit having two or more corresponding sections. The plurality of configurable units is arranged in a serial arrangement to form a chain of sections of the configurable units. A data bus is connected to the plurality of configurable units which communicates data at a clock rate. The chain of sections is to receive and write a series of tensors at the clock rate at a first end section of the chain of sections, and sequentially propagate the series of tensors through individual sections within the chain of sections at the clock rate. The chain of sections is to output the series of tensors at a second end section of the chain of sections. The chain of sections is to also output the series of tensors at an intermediate section of the chain of sections.