Reconfigurable RF Chip Architecture for Algorithm Flexibility
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Solution Overview
Problem
Existing radio frequency chips face challenges with low hardware resource utilization and efficiency due to fixed operation functions and limited flexibility, making them unsuitable for updated algorithm requirements, leading to high power consumption and re-development costs.
Innovation Solution
A radio frequency chip with a configuration interface, interconnection bus, and processor that allows for flexible reconfiguration of operation units to support different operation functions, enabling software customization and efficient hardware resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated hardware logic circuit is used as a direct implementation carrier on a customized chip, then operation speed is improved and energy efficiency is improved, but adaptability deteriorates because the operation unit only supports fixed operation functions and cannot update the mathematical operation function
Solution Approach 1:
The patent implements dynamic reconfigurability by allowing the operation unit to switch between different mathematical operation functions (e.g., complex multiplication, convolution, correlation) through configuration interfaces. The hardware logic circuit can be dynamically reprogrammed to support different algorithms without physical reconfiguration, resolving the contradiction between fixed high-speed hardware and flexible algorithm support.
Solution Approach 2:
The operation unit is designed with multi-functionality to perform various mathematical operations including complex multiplication, convolution, and correlation. By integrating multiple operation capabilities into a single hardware unit that can be configured via software, the system achieves both high operation speed and broad algorithm compatibility without requiring separate dedicated circuits for each function.
2Adaptability or versatility
If FPGA is used to implement the algorithm function, then adaptability is improved because the algorithm can be reprogrammed to meet new mathematical operation model needs, but energy efficiency deteriorates, operation speed deteriorates, and power consumption increases
Solution Approach 1:
Instead of using expensive FPGA resources for all operations, the patent employs a more efficient custom-designed hardware logic circuit that can be reprogrammed through software configuration. This approach provides FPGA-like reprogrammability but with significantly improved energy efficiency and operation speed by using optimized hardware architecture rather than general-purpose FPGA logic.
Solution Approach 2:
The patent replaces the mechanical reconfiguration approach of FPGA with a software-controlled configuration interface that directs pre-optimized hardware logic circuits. This substitution allows the system to maintain the flexibility of reprogramming while achieving the performance of dedicated hardware, as the hardware logic is optimized for specific mathematical operations rather than general-purpose logic.
3Productivity
If existing reconfigurable operation technology is used with regular high-density parallel operations, then operation speed is improved, but hardware resource utilization deteriorates due to low efficiency of single operation units compatible with specific mathematical operation functions
Solution Approach 1:
The patent implements dynamic function allocation where operation units can switch between different mathematical operations (complex multiplication, convolution, correlation, etc.) based on configuration data. This dynamic reconfiguration allows the same hardware resources to be efficiently utilized for different algorithms, improving both operation speed and hardware resource utilization by eliminating idle specialized units.
Solution Approach 2:
The system changes operational parameters through configuration interfaces, allowing operation units to adjust their functional behavior without physical modification. By changing configuration parameters rather than hardware structure, the system achieves high-speed operation while maximizing hardware resource utilization across different algorithm requirements.
Data Source
AI summary
The present application relate to the technical field of mobile communication, and in particular to a radio frequency chip, an algorithm reconstruction method and a computer-readable storage medium. The radio frequency chip includes a configuration interface, an interconnection bus, a processor and at least two operation units. Each operation unit is provided with different operation functions. The configuration interface is connected to the processor, and is configured to transmit the received routing information and the configuration data to the processor. The routing information and the configuration data are determined according to a target operation function of the radio frequency chip. The interconnection bus is communicated with each operation unit and is connected to the processor, and is configured to adjust an input and output relationship between each operation unit.