Reconfigurable Server Bandwidth via PCIe Switch and FPGA
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Solution Overview
Problem
Current server configurations in data centers, particularly those using leaf-spine topology, face inefficiencies due to limited bandwidth between the CPU and near-memory modules, leading to reduced performance for tasks requiring access to near-memory storage.
Innovation Solution
The integration of a programmable logic device (PLD), such as a field programmable gate array (FPGA), to enhance connectivity between the CPU and near-memory modules, along with direct connections between the near-memory module and the switch, utilizing PCIe channels and expander modules to increase bandwidth and reduce bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a SATA controller is used to connect the processor to the near-memory module, then the server design is simple and cost-effective, but the bandwidth is relatively limited
Solution Approach 1:
The patent changes the interface parameter from SATA to PCIe, which fundamentally alters the bandwidth capability. The PCIe interface provides significantly higher theoretical bandwidth than SATA, enabling fast access to near-memory modules while maintaining server design simplicity through modular implementation.
2Quantity of substance
If a direct connection between the processor array and near-memory accelerator modules is implemented, then the bandwidth is increased, but the device complexity increases
Solution Approach 1:
The patent introduces a PCIe switch as an intermediary component that manages the connectivity between the processor array and multiple near-memory accelerator modules. This mediator approach allows high bandwidth direct connections while organizing the complexity through a structured switching architecture that simplifies signal routing and resource management.
Solution Approach 2:
The patent segments the memory subsystem into separate near-memory accelerator modules, each with its own PLD and PCIe connection. This segmentation allows independent optimization of each module while distributing the connectivity complexity across multiple standardized interfaces rather than requiring a monolithic high-complexity connection system.
3Adaptability or versatility
If a PCIe expander module is added to provide alternative paths, then the connectivity and bandwidth are improved, but the device complexity increases
Solution Approach 1:
The patent implements dynamic connectivity through the PCIe expander module that can configure alternative signal paths between the processor array and near-memory modules. This dynamic path selection allows the system to adapt to different operational requirements and failure conditions, providing connectivity flexibility without requiring permanent complex wiring for every possible scenario.
Data Source
AI summary
A reconfigurable server includes improved bandwidth connection to adjacent servers and allows for improved access to near-memory storage and for an improved ability to provision resources for an adjacent server. The server includes processor array and a near-memory accelerator module that includes near-memory and the near-memory accelerator module helps provide sufficient bandwidth between the processor array and near-memory. A hardware plane module can be used to provide additional bandwidth and interconnectivity between adjacent servers and/or adjacent switches.