Reconfigurable Processor Simulator Using Precomputed Routing Queues
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Solution Overview
Problem
Simulators for Coarse-Grained Reconfigurable Architectures (CGRA) face complexity and reduced simulation speed due to the need to model and monitor numerous interconnection logics, which limits their ability to provide cycle accuracy and efficient performance debugging.
Innovation Solution
A simulator that models routing paths between functional units as queues, representing routing delays and stage information based on modulo scheduling, allowing for the simulation of binary files and reducing the complexity of interconnection components by using an abstracted architecture model that maps functional units and their operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the simulator models and monitors numerous interconnection logics to ensure cycle accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent creates a simplified copy of the interconnection logic behavior through pre-computed routing information. Instead of modeling the actual complex interconnection logics, the simulator uses a simplified data structure that copies only the essential routing delay characteristics, allowing cycle accuracy without the full complexity of the original interconnection model
Solution Approach 2:
The patent performs preliminary computation of routing information during compilation or setup phase. The routing delays between functional units are pre-calculated and stored in a data structure before simulation begins, eliminating the need to dynamically compute or monitor complex interconnection logics during the simulation process itself
2Measurement precision
If the simulator monitors numerous interconnection logics to ensure accurate performance debugging, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The simulator uses a simplified copy of routing behavior that captures only the essential timing characteristics needed for performance debugging. This copied model maintains measurement precision for debugging purposes while being computationally lightweight enough to maintain high simulation speed
Solution Approach 2:
All routing delay calculations are performed in advance during compilation or setup. The simulation process itself only needs to read pre-computed routing information from a data structure, making each simulation cycle fast while still providing accurate performance debugging data
3Measurement precision
If the simulator uses a detailed model of interconnection logics, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent uses a simplified copy of the interconnection model that retains only the timing-critical routing delay information. This copied model provides sufficient simulation accuracy for performance evaluation while requiring minimal computation time during the simulation process
Solution Approach 2:
The computationally intensive routing delay calculations are performed beforehand during compilation or setup phase. The actual simulation runs quickly by simply reading from the pre-computed routing information stored in a data structure, dramatically reducing simulation time while maintaining accuracy
Data Source
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AI summary
A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.