Statically Reconfigurable Soft-Processor Cores for Hardware Acceleration
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Solution Overview
Problem
The conventional building of hardware accelerators is a labor-intensive and resource-intensive process, requiring unique configurations for each task, which leads to increased costs and inefficiencies.
Innovation Solution
A system and method for building hardware accelerators that utilize a code analyzer to repeatedly perform static and dynamic analyses on software programs and machine code, determining the necessary resources and configurations for executing specific algorithms on hardware accelerators, thereby reducing hardware resources and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to build hardware accelerators with unique configurations for each task, then task-specific performance is improved, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent implements a universal hardware accelerator platform that can execute multiple different algorithms through software programming rather than requiring unique hardware configurations for each task. The system uses a configurable processor architecture that can be programmed via HDL code to perform various functions, eliminating the need for separate dedicated hardware designs for each algorithm while maintaining task-specific optimization capabilities.
Solution Approach 2:
The system allows dynamic configuration of hardware accelerator parameters through software-based HDL programming. By changing the configuration parameters and algorithmic descriptions in the HDL code, the same physical hardware can be reconfigured to execute different algorithms with optimized performance characteristics, avoiding the complexity of designing unique hardware for each task.
2Productivity
If hardware accelerators are customized for specific tasks, then processing efficiency is improved, but manufacturing costs and resource consumption increase
Solution Approach 1:
The patent creates a universal hardware accelerator platform that maintains processing efficiency through software-based configuration rather than physical customization. A single manufacturing process produces the universal platform, which then achieves task-specific optimization through programmable HDL configurations, significantly reducing manufacturing costs compared to producing custom-hardware accelerators for each algorithm.
Solution Approach 2:
Instead of manufacturing unique hardware designs for each algorithm, the system creates software-based HDL copies of algorithmic logic that run on the universal hardware platform. This allows efficient execution of specific algorithms through virtual copies of processing logic rather than physical hardware duplication, reducing manufacturing complexity and cost.
3Productivity
If static analysis and dynamic analysis are repeatedly performed on software programs, then hardware resource optimization is improved, but analysis time and computational overhead increase
Solution Approach 1:
The system performs static and dynamic analyses of software programs in advance during the HDL configuration generation phase, before the hardware accelerator is deployed. By conducting these analyses preliminarily to determine optimal resource allocation and configuration parameters, the system achieves hardware resource optimization without requiring repeated analyses during runtime, thus minimizing analysis time overhead during actual operation.
Data Source
AI summary
A system and method for building a hardware accelerator. The system has at least one processor including at least one core configured to perform based on machine code an operation for a specific algorithm of the hardware accelerator. The system has a code analyzer for reconfiguring the at least one processor to execute with the machine code the specific algorithm. The code analyzer is configured to repeatedly execute at least one of a) a static analysis on a software program for performance of the specific algorithm and b) a dynamic analysis regarding the machine code on different input sets of data. The code analyzer is configured to analyze results of the static analysis or the dynamic analysis to determine a configuration of the machine code for execution of the specific algorithm on the hardware accelerator.