Reconfigurable SRAM Block Assignment for SoC Adaptability
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Solution Overview
Problem
The existing systems on chip (SoCs) with static random access memory (SRAM) face challenges in adapting to changing performance demands and varying user requirements, leading to costly design and manufacturing inefficiencies due to fixed SRAM layouts that cannot be readily reconfigured.
Innovation Solution
A system on chip with a reconfigurable SRAM module that dynamically assigns and connects multiple SRAM blocks to various components based on different operational phases, allowing for SRAM blocks to be used as cache, temporary storage, or emulate read-only memory, thereby optimizing SRAM usage and reducing overall SRAM size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SRAM layout is fixed during manufacturing, then manufacturing process is simple and cost-effective, but the system cannot adapt to changing performance demands and different user requirements
Solution Approach 1:
The patent implements dynamic reconfiguration of SRAM blocks by introducing a control module that can dynamically assign different SRAM blocks to different components based on operational phase. The connection module dynamically connects SRAM blocks to components according to current performance demands, transforming the static SRAM layout into a dynamic, adaptable structure that can change during system operation.
Solution Approach 2:
The patent makes SRAM blocks multi-functional by allowing the same physical SRAM block to serve different purposes at different times. Through the control module, SRAM blocks can be assigned to different components (e.g., processor cache, DSP storage, protocol stack buffering) based on operational phase, enabling a single SRAM infrastructure to support multiple functions and varying performance requirements.
2Adaptability or versatility
If different SoCs are designed for different performance objectives requiring different SRAM amounts, then each variant can be optimized for its specific use case, but designing and manufacturing multiple variants is costly
Solution Approach 1:
The patent creates a universal SRAM allocation mechanism where a single SRAM block can serve multiple components and multiple performance objectives through dynamic reconfiguration. The control module enables the same physical SRAM infrastructure to be allocated differently based on operational phase, eliminating the need to manufacture separate SoC variants for different performance requirements.
Solution Approach 2:
The patent introduces dynamic allocation capabilities that allow SRAM blocks to be reassigned during system operation. The connection module dynamically establishes connections between SRAM blocks and components based on current performance demands, enabling cost-effective manufacturing of a single SoC variant that can adapt to different performance objectives without requiring multiple hardware designs.
3Productivity
If SRAM blocks are statically assigned to components, then the assignment is simple and stable, but the system cannot dynamically optimize SRAM usage based on changing operational phases
Solution Approach 1:
The patent implements feedback-based dynamic allocation where the control module monitors operational phase and performance demands. Based on this feedback, the control module adjusts SRAM block assignments to optimize productivity. The system can detect when different components need different amounts of SRAM access and dynamically reassign blocks accordingly, creating a closed-loop optimization system.
Solution Approach 2:
The patent transforms static SRAM assignments into dynamic assignments through the introduction of a control module that actively manages SRAM block allocation. The connection module dynamically establishes and re-establishes connections between SRAM blocks and components based on operational phase, enabling the system to adapt SRAM usage patterns to current performance demands and optimize productivity.
Data Source
AI summary
A system on chip includes electrical components and a first memory including memory blocks. A method of operating the system on chip includes generating an assignment of the memory blocks to the electrical components. The generating includes, initially, during a development phase of the system on chip, generating the assignment so that selected memory blocks of the memory blocks are assigned to first selected electrical components of the electrical components as emulated read-only memory. The generating includes, subsequently, during an operational phase of the system on chip, modifying the assignment so that one or more of the selected memory blocks are re-assigned to second selected electrical components of the electrical components as cache memory. The method also includes, according to the assignment, dynamically creating electrical connectivity between the memory blocks and the electrical components.