Reconfigurable SSD Storage Pool Dynamic Byte-to-Block Conversion

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Solution Overview

Problem

Byte addressable NV storage regions in SSDs degrade over time due to excessive bit flipping, leading to reduced storage capacity and increased manufacturing costs, as they become unusable when error correction limits are exceeded, and manufacturing difficulties result in lower yields and higher costs.

Innovation Solution

An SSD system that dynamically reclassifies byte addressable NV storage regions as block addressable NV storage regions when degradation is detected, using a controller to monitor storage capacity and update metadata registers, allowing continued utilization of storage regions as block addressable NV storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If byte addressable NV storage regions are used in SSDs, then storage flexibility and write performance are improved, but storage regions degrade prematurely due to excessive bit flipping and become unusable when error correction limits are exceeded

Engineering Contradiction:
Improvestorage flexibilityVSAvoidstorage region usability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent implements dynamic reconfiguration of storage regions, allowing the SSD controller to change storage regions from byte addressable mode to block addressable mode when degradation is detected. This dynamic adaptation enables the system to maintain reliability by switching operational modes based on real-time storage region health status, thereby resolving the contradiction between initial flexibility and long-term usability.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If byte addressable NV storage regions are used in SSDs, then storage flexibility is improved, but manufacturing yields decrease and costs increase due to high number of faulty memory cells

Engineering Contradiction:
Improvestorage flexibilityVSAvoidmanufacturing yield
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The patent changes the operational parameters of storage regions dynamically. Storage regions that fail manufacturing tests with high defect rates are initially configured as byte addressable but are automatically reconfigured to block addressable mode after degradation detection. This parameter change allows manufacturers to salvage defective regions that would otherwise be discarded, improving manufacturing yields while maintaining storage flexibility through adaptive reconfiguration.

Inventive Principle:
Principle #35Parameter changes

3Duration of action of stationary object

If wear leveling and logical to physical address translation are performed on byte addressable NV memory, then storage longevity is improved, but read and write latencies increase to unacceptable levels

Engineering Contradiction:
Improvestorage longevityVSAvoidaccess latency
Core Design Contradiction:
Duration of action of stationary objectVSLoss of time

Solution Approach 1:

The patent segments storage regions into different operational modes based on their health status and access patterns. By dividing the storage system into healthy byte addressable regions and degraded block addressable regions, the system can apply wear leveling selectively to block addressable regions without impacting the performance of byte addressable regions. This segmentation allows longevity extensions for degraded regions while maintaining low latency for active byte addressable operations.

Inventive Principle:
Principle #1Segmentation

4Reliability

If stronger ECC logic is applied to correct bit errors in byte addressable NV storage, then storage reliability is improved, but manufacturing costs increase and storage access latency becomes unacceptable

Engineering Contradiction:
Improveerror correction capabilityVSAvoidECC logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic switching of error correction strategies. Instead of applying strong ECC logic continuously to all byte addressable regions, the system monitors degradation and dynamically switches degraded regions to block addressable mode where different error correction approaches are used. This dynamic approach reduces the need for complex strong ECC logic in byte addressable regions while maintaining overall reliability through adaptive error management.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12026388B2Reconfigurable SSD storage pool
Publication Date: 2024.07.02 KIOXIA CORP
  • US12026388B2 patent drawing
  • US12026388B2 patent drawing
  • US12026388B2 patent drawing

AI summary

A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.