Reconfigurable Storage Device for Near-Storage Data Acceleration

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Solution Overview

Problem

Existing storage systems face challenges in efficiently processing data-intensive operations, leading to increased latency and resource overutilization in host devices due to the need to transfer large amounts of data for processing.

Innovation Solution

A storage device with a reconfigurable integrated circuit that includes static and dynamic logic blocks, allowing for near-storage acceleration of latency-critical and throughput-oriented operations. The reconfigurable integrated circuit can dynamically reconfigure logic operations based on the pipeline workflow, optimizing resource utilization and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data-intensive operations are handled by the host device, then processing capability is improved, but data transfer volume increases and latency increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts data-intensive operations from the host device and relocates them to the storage device. The storage device includes a reconfigurable logic array that can be configured to perform filtering, sorting, grouping, and other data-intensive operations directly on stored data, eliminating the need to transfer large volumes of data to the host device for processing.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a reconfigurable logic array as an intermediary component between the storage memory and the host device. This logic array acts as a mediator that performs data processing operations within the storage device, reducing the data transfer burden on the host device while maintaining processing capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If data-intensive operations are handled by the host device, then processing flexibility is improved, but resource utilization of host device increases excessively

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidhost device resource utilization
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent implements a reconfigurable logic array that can dynamically change its configuration based on the specific data-intensive operation required. The logic array can be reconfigured to perform different operations such as filtering, sorting, grouping, and aggregation, providing processing flexibility while keeping the operational logic within the storage device to reduce host device resource utilization.

Inventive Principle:
Principle #15Dynamics

3Loss of substance

If storage device performs data-intensive operations, then data transfer volume is reduced, but device complexity increases

Engineering Contradiction:
Improvedata transfer volumeVSAvoidstorage device complexity
Core Design Contradiction:
Loss of substanceVSDevice complexity

Solution Approach 1:

The patent implements a universal reconfigurable logic array that can perform multiple data-intensive operations including filtering, sorting, grouping, and aggregation. This single multi-functional component reduces the need for separate dedicated hardware for each operation, thereby reducing overall device complexity while enabling the storage device to perform various data-intensive operations and reduce data transfer volume.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12265736B2Latency and throughput centric reconfigurable storage device
Publication Date: 2025.04.01 SAMSUNG ELECTRONICS CO LTD
  • US12265736B2 patent drawing
  • US12265736B2 patent drawing
  • US12265736B2 patent drawing

AI summary

A storage device includes: a storage controller to receive data from a host device, and to store the data in storage memory; and a reconfigurable integrated circuit communicably connected to the storage controller, and to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit including: a first logic block to execute a static logic operation from among the logic operations; a second logic block to execute one or more dynamic logic operations from among the logic operations; and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.