Partially Reconfigurable Switch Using Cyclic Bitstream Pipelining
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The development of FPGA-based SoCs is challenging due to communication limitations among multiple hardware and software processors, which are typically addressed by Network-on-Chip (NoC) but come with high complexity and resource utilization, and partially reconfigurable switches face issues with bandwidth and implementation complexity.
Innovation Solution
A method and system utilizing a partially reconfigurable switch with cyclic-pipeline application of stored connection configurations, eliminating reconfiguration overhead and arbitration, and implementing a lossless K-of-N switch/crossbar interconnect with pipelined partial bitstreams applied in a synchronous manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Network-on-Chip (NoC) is used to address communication limitations among multiple processors, then communication performance is improved, but device complexity and resource utilization increase
Solution Approach 1:
The patent segments the NoC functionality into a partially reconfigurable switch that can be dynamically divided into multiple independent crossbar switches. This segmentation allows the system to achieve NoC-level communication performance for specific connection patterns while using fewer resources than a full NoC implementation, thereby reducing device complexity while maintaining improved communication performance.
Solution Approach 2:
The patent implements dynamic reconfigurability where the switch can be reconfigured between different connection patterns (broadcast, multicast, unicast) based on communication requirements. This dynamic adaptation allows the system to optimize communication performance for different workloads without permanently allocating resources for all possible communication scenarios, thus reducing overall device complexity and resource utilization.
2Adaptability or versatility
If traditional crossbar switch is used to support N-concurrent source-to-sink interconnects, then adaptability is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent applies partial reconfiguration by implementing only the subset of crossbar connections that are currently needed rather than maintaining full N-concurrent interconnect capability at all times. The switch can be partially configured to support specific connection patterns (e.g., K-of-N connections) based on instantaneous communication requirements, reducing device complexity while maintaining the adaptability to reconfigure for different patterns when needed.
3Adaptability or versatility
If reconfiguration is implemented in partially reconfigurable switches, then adaptability is improved, but reconfiguration overhead and arbitration requirements increase
Solution Approach 1:
The patent implements preliminary action by pre-calculating and storing optimal connection configurations for common communication patterns in lookup tables. When a reconfiguration is needed, the system can quickly retrieve pre-computed configuration data rather than performing complex real-time arbitration and configuration calculations, thereby reducing reconfiguration overhead while maintaining high adaptability to different communication patterns.
Data Source
AI summary
A system and method of configuring a partially reconfigurable switch includes a pipelined partially reconfigurable switch interconnect may include a desired subset of connections in a switch interconnect, a partial bitstream defined for each of the desired subset of connections stored in a memory such as SRAM serving as a buffer, and a controller for cyclically applying the partial bitstream to the switch interconnect. The controller may determine a connection instance and duration for each client access of the switch interconnect in a synchronous manner. A clear to send (CTS), receive data (RD), destination address, and source address at each client may be sent with each partial bitstream for each desired subset of connections. The partially reconfigurable switch and a plurality of partially reconfigurable slot clients may be formed in a silicon backplane.