Reconfigurable Systolic Array Layout for Variable CNN Matrix Sizes
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Solution Overview
Problem
Existing systolic arrays for convolutional-neural-network operations have a fixed matrix size, limiting their flexibility and efficiency in performing convolution operations.
Innovation Solution
A systolic array that can reconfigure its matrix size by dividing into partial systolic arrays, allowing for variable matrix dimensions and improved convolution operations through control signals and memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the systolic array uses a fixed matrix size, then the hardware structure is simple and easy to manufacture, but the adaptability to different input and weight data sizes is limited
Solution Approach 1:
The systolic array is divided into multiple processing elements (PEs) arranged in a matrix configuration, where each PE can independently process sub-sections of the input and weight matrices. This segmentation allows the fixed hardware structure to handle variable-sized data by distributing different portions of the computation across different PEs, thereby achieving adaptability without changing the overall hardware architecture.
Solution Approach 2:
Each processing element in the systolic array is designed with universal functionality to perform multiply-accumulate operations regardless of the input matrix size. The PEs can be dynamically configured through control signals to process different dimensions of input and weight data, making the fixed hardware structure capable of handling multiple data sizes and formats without requiring physical reconfiguration.
2Productivity
If the systolic array divides into partial systolic arrays, then the adaptability to different data sizes is improved, but the device complexity increases
Solution Approach 1:
The systolic array implements dynamic configuration where processing elements can be selectively activated or deactivated based on the size of the input and weight matrices. Control signals dynamically adjust the operational state of each PE, enabling the array to optimize its computational throughput for different data sizes by activating only the necessary subset of PEs, thereby maintaining high productivity while managing complexity through controlled activation patterns.
3Productivity
If the matrix size is increased to handle larger data, then the computational performance is improved, but the area occupied by the systolic array increases
Solution Approach 1:
The systolic array employs partial action by activating only the necessary number of processing elements based on the actual size of the input and weight matrices. Instead of always utilizing the full matrix capacity, the system dynamically activates a subset of PEs proportional to the computation required, thereby achieving high computational throughput for smaller data sizes without occupying the full hardware resources, and maintaining area efficiency while preserving the capability for high-performance computation when needed.
Data Source
AI summary
A systolic array and an accelerator including the same are disclosed. The systolic array may include n×n processing elements disposed in an n×n matrix (n being an integer equal to or more than at least 4), wherein the n×n processing elements perform a first convolution operation on first input data of row vectors of a first input n×n matrix and first weight data of column vectors of a first weight n×n matrix to generate n first output data, or each of at least k partial systolic arrays (k being an integer equal to or more than at least 4) constituted by dividing the n×n processing elements includes m×m processing elements disposed in an m×m matrix (m being an integer less than n and equal to or more than at least 2).