Reconfigurable TDC in Digital PLLs for Low-Power Phase Lock
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital phase-locked loops (PLLs) face inefficiencies in power consumption due to the need for extensive delay elements and comparators during phase capture, which continue to operate even after phase lock is achieved, leading to increased power usage.
Innovation Solution
Implementing a digital PLL with a time-to-digital converter (TDC) that includes serially-coupled delay elements and comparators, which are fully enabled during phase locking but selectively disabled after achieving phase lock, reducing power consumption by powering down all but a subset of these elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all delay elements and comparators are enabled during phase capture, then phase locking reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the TDC structure configurable between two states: a first configuration during phase capture where all delay elements and comparators are enabled for reliable phase locking, and a second configuration during locked operation where only a subset remains active to reduce power consumption. The control circuit dynamically switches between these configurations based on lock detection status.
Solution Approach 2:
The patent applies local quality by enabling different portions of the TDC at different times. During phase capture, the entire TDC is active; during locked operation, only a subset of delay elements and comparators remains enabled. This localized activation optimizes power consumption while maintaining necessary functionality.
2Measurement precision
If a large number of delay elements are used during phase capture, then phase locking accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses dynamics to configure the TDC with a variable number of active delay elements based on operational phase. During phase capture, all delay elements are enabled for high measurement precision. During locked operation, the control circuit reduces the number of active delay elements to a subset, thereby reducing device complexity and power consumption while maintaining adequate precision through the remaining elements.
3Reliability
If all comparators remain active after phase lock, then phase error detection capability is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by selectively enabling only a subset of comparators during locked operation rather than keeping all comparators active. The control circuit determines which comparators to disable based on the detected phase lock condition, thereby maintaining sufficient phase error detection capability with reduced power consumption from the deactivated comparators.
Solution Approach 2:
The patent applies discarding and recovering by temporarily disabling (discarding) certain comparators after phase lock is achieved to reduce power consumption. When phase capture is needed again, these comparators can be re-enabled (recovered), allowing the system to cycle between low-power and high-performance states as needed.
Data Source
AI summary
A digital PLL is disclosed. In one embodiment, the digital PLL includes a TDC coupled to receive a reference clock signal and feedback signal. The TDC includes a chain of serially-coupled delay elements. An oscillator in the PLL is configured to generate a periodic output signal. A divider is coupled to receive the periodic output signal and generate the feedback signal provided to the TDC. The digital PLL also includes a control circuit. During a phase-locking procedure, each of the serially-coupled delay elements is enabled for fast phase capture. However, once phase-lock has been detected by observing TDC output code, the control circuit is adaptively configured to disable all but a subset of the delay elements for saving power.