Re-configurable Test Circuit for Automated Equipment

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Solution Overview

Problem

The increasing complexity of devices under test, particularly systems on a chip, poses challenges in creating appropriate test programs due to unpredictable communication initiation and timing, making it difficult for conventional automated test equipment to effectively test devices that can autonomously establish communication protocols.

Innovation Solution

A re-configurable test circuit with a programmable logic device and a test processor that provides adjustable-timing signals to interface with devices-under-test, implementing a state machine dependent on input signals to manage signal processing and timing accurately, allowing for flexible protocol behavior and improved timing accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional automated test equipment uses predetermined test vectors and fixed timing, then the test equipment structure is simple and easy to operate, but it cannot handle unpredictable device communication initiation and timing

Engineering Contradiction:
Improveability to handle unpredictable device communicationVSAvoidtest equipment structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic timing adjustment by allowing the test equipment to receive timing information from the device-under-test and adapt its test sequences accordingly. The test processor can modify test timing based on actual device behavior, transforming the system from static to dynamic operation. This resolves the contradiction by enabling adaptability to unpredictable communication timing while maintaining a relatively simple overall structure through software-based timing adjustment rather than complex hardware reconfiguration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent incorporates feedback mechanisms where the device-under-test provides timing information back to the test processor. This feedback loop allows the test equipment to observe actual device communication patterns and adjust test sequences in response. The feedback mechanism enables the system to handle unpredictable device initiation and timing by continuously adapting based on observed behavior, resolving the adaptability-complexity contradiction through intelligent control rather than structural complexity.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If the test equipment implements programmable protocol behavior and adjustable timing, then timing accuracy and adaptability improve, but the device complexity increases

Engineering Contradiction:
Improvetiming accuracyVSAvoidtest circuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a universal timing adjustment mechanism that serves multiple functions: it provides precise timing control for test sequences, adapts to different communication protocols, and handles unpredictable device timing behavior. By designing a flexible timing architecture that can be configured for different test scenarios rather than dedicated hardware for each function, the system achieves high timing accuracy and protocol adaptability without proportionally increasing structural complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent utilizes parameter changes in timing characteristics to achieve adaptability. Instead of redesigning hardware for different protocols, the system adjusts timing parameters such as delay values, clock frequencies, and sequence durations based on protocol requirements and device behavior. This parameter-based approach enables precise timing control across different communication protocols while avoiding the complexity of hardware reconfiguration for each protocol variant.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If conventional test equipment uses fixed test sequences, then the equipment is easy to operate and maintain, but it cannot accommodate devices that autonomously establish communication protocols

Engineering Contradiction:
Improvehandling autonomous device communicationVSAvoidtest program creation
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The patent implements preliminary configuration of test parameters and protocols before actual testing begins. The test processor is pre-configured with adjustable timing parameters and protocol settings that can be quickly adapted to different devices. This preliminary setup enables operators to handle autonomous device communication without creating complex test programs from scratch, as the system can be rapidly configured for specific device types through pre-established parameter templates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables the test equipment to automatically adapt to device behavior through self-service mechanisms. The system can autonomously observe device communication patterns, extract timing information, and automatically adjust test sequences without requiring extensive manual programming. This self-service capability maintains ease of operation by reducing manual test program creation while simultaneously providing adaptability to handle autonomous device communication protocols.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8838406B2Re-configurable test circuit, method for operating an automated test equipment, apparatus, method and computer program for setting up an automated test equipment
Publication Date: 2014.09.16 ADVANTEST CORP
  • US8838406B2 patent drawing
  • US8838406B2 patent drawing
  • US8838406B2 patent drawing

AI summary

A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.