Reconfigurable Test IP Architecture for Semiconductor ATE
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Solution Overview
Problem
Current automatic test equipment (ATE) systems for semiconductors are limited by fixed instrument architectures that are not reconfigurable and lack native links to the design environment, making them inefficient and inflexible in handling the diverse and complex interfaces of modern semiconductor devices, particularly across pre-silicon simulation, post-silicon validation, and production testing phases.
Innovation Solution
A Test IP (TIP) based ATE instrument architecture that is reconfigurable and natively linked with the design simulation/verification environment, allowing for seamless integration across phases and supporting various protocols, including digital, analog, and RF interfaces, through the use of Reconfigurable Test Instruments (RTIs) and Protocol Engines that match specific device interfaces and protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed architecture ATE instruments are used, then device under test coverage is limited, but hardware and software complexity is reduced
Solution Approach 1:
The patent implements a universal ATE instrument architecture using FPGA-based protocol engines that can be configured to support multiple device interfaces and protocols (I2C, SPI, UART, USB, etc.). This single multi-functional instrument replaces the need for multiple specialized fixed-architecture instruments, achieving universal coverage across different DUT types while maintaining manageable complexity through standardized hardware platforms and configurable software layers.
Solution Approach 2:
The system employs dynamically reconfigurable FPGA logic that allows the protocol engine to adapt its behavior based on the specific DUT interface requirements. The architecture supports runtime configuration of communication protocols and interface parameters, enabling the same hardware to dynamically switch between different testing scenarios without physical reconfiguration, thus improving versatility without proportionally increasing complexity.
2Measurement precision
If specialized infrastructure is used for each testing phase, then testing precision is improved, but cost and operational complexity increase
Solution Approach 1:
The patent implements a universal ATE instrument architecture using FPGA-based protocol engines that can be configured to support multiple device interfaces and protocols (I2C, SPI, UART, USB, etc.). This single multi-functional instrument replaces the need for multiple specialized fixed-architecture instruments, achieving universal coverage across different DUT types while maintaining manageable complexity through standardized hardware platforms and configurable software layers.
Solution Approach 2:
The system employs dynamically reconfigurable FPGA logic that allows the protocol engine to adapt its behavior based on the specific DUT interface requirements. The architecture supports runtime configuration of communication protocols and interface parameters, enabling the same hardware to dynamically switch between different testing scenarios without physical reconfiguration, thus improving versatility without proportionally increasing complexity.
3Ease of operation
If fixed protocol support is implemented, then ease of operation is improved, but adaptability to new interfaces deteriorates
Solution Approach 1:
The system employs dynamically reconfigurable FPGA logic that allows the protocol engine to adapt its behavior based on the specific DUT interface requirements. The architecture supports runtime configuration of communication protocols and interface parameters, enabling the same hardware to dynamically switch between different testing scenarios without physical reconfiguration, thus improving versatility without proportionally increasing complexity.
Solution Approach 2:
The patent utilizes parameter-based configuration where the FPGA protocol engine accepts configurable parameters defining the specific interface protocol to be used. By changing these parameters (protocol type, data width, clock speed, etc.), the system can adapt to new interfaces without hardware modification. This parameter-driven approach maintains ease of operation through standardized configuration interfaces while achieving high adaptability to diverse and emerging device interfaces.
Data Source
AI summary
A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus. The test program stored on the controller, and the controller, instantiates interfaces and protocols, and certain process transactions to support the protocols, into FPGAs, to match device interfaces for each DUT, to execute test sequences.