Reconfigurable Test Architecture for Multi-Die Chip Validation
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Solution Overview
Problem
Existing test methodologies are inadequate for efficiently testing multiple dies packaged together on a single substrate, as they were primarily developed for single die testing, leading to increased test time and costs.
Innovation Solution
A reconfigurable test architecture that allows for concurrent die-level testing of multiple dies and chip-level testing, including die-to-die and boundary I/O tests, by utilizing a test circuit with scan cells, TAP controllers, and multiplexers to form a single scan chain for external testers to perform various tests efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-die test methodologies are used for multi-die chips, then testing can be performed with existing simple equipment, but test time increases and productivity decreases
Solution Approach 1:
The patent merges multiple individual die test circuits into a unified test architecture where scan chains from multiple dies are interconnected to form a consolidated testing system. This allows simultaneous testing of multiple dies through shared test resources, dramatically improving productivity and reducing test time compared to traditional sequential single-die testing approaches.
Solution Approach 2:
The test architecture provides multi-functionality by enabling both individual die-level testing and integrated chip-level testing through a single unified system. The same test circuit can configure scan chains to test internal logic on individual dies or test inter-die connections and boundary I/O, eliminating the need for separate testing equipment and procedures.
2Adaptability or versatility
If separate test circuits are used for each die, then each die can be tested independently, but device complexity and testing costs increase
Solution Approach 1:
The test architecture employs dynamic reconfigurability where scan chain connections between dies can be programmatically adjusted based on testing requirements. Multiplexers and control logic allow the system to dynamically reconfigure the test topology, enabling independent die testing when needed while also supporting integrated chip-level testing, thus providing adaptability without permanent complexity.
3Loss of time
If concurrent testing of multiple dies is implemented, then test time is reduced, but test circuit complexity and manufacturing difficulty increase
Solution Approach 1:
The test architecture segments the chip into multiple independently testable die units, each with its own scan chain and test access port. This segmentation allows concurrent testing of individual dies while maintaining the ability to test inter-die connections by connecting the segmented scan chains in series, thus reducing test time without requiring completely new manufacturing approaches.
Data Source
AI summary
Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.