Reconfigurable Time Delay Units for Phased Array Antennas

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Solution Overview

Problem

Existing phased array antennas require custom-designed time delay units, which are expensive, non-reconfigurable, and have long lead times, making it difficult to support multiple time delay level requirements.

Innovation Solution

A phased array antenna with reconfigurable time delay units that include a circuit substrate with multiple delay circuits coupled in series, and external bypass connections to configure overall time delays, allowing for interchangeable configurations between high and low delay levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If custom-designed time delay units are used for each time delay level requirement, then the phased array antenna can support multiple time delay levels, but the cost increases and lead times lengthen

Engineering Contradiction:
Improvesupport multiple time delay levelsVSAvoidcost and lead time
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent applies universality by designing a single time delay unit that can perform multiple functions - supporting both high and low time delay levels through reconfigurable delay circuits. The unit uses switches to dynamically reconfigure the signal path, allowing the same hardware to adapt to different time delay requirements without requiring separate custom-designed units for each level, thereby reducing cost and lead time while maintaining versatility

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements dynamics through reconfigurable delay circuits that can change their configuration in real-time. Switches are used to dynamically reconfigure the signal path between different delay circuits, enabling the time delay unit to adapt its characteristics based on operational requirements. This dynamic reconfiguration capability allows a single unit to replace multiple static custom-designed units

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If multiple custom time delay unit designs are created to support different time delay level requirements, then all requirements are met, but device complexity increases

Engineering Contradiction:
Improvesupport different time delay level requirementsVSAvoidnumber of time delay unit designs
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent reduces device complexity by creating a universal time delay unit design that handles multiple time delay level requirements. Instead of maintaining separate custom designs for high and low delay levels, the universal unit uses reconfigurable delay circuits and switches to accommodate all requirements through a single standardized design, simplifying the overall system architecture

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies segmentation by dividing the time delay function into modular reconfigurable delay circuits that can be selectively activated. The signal path is segmented into multiple delay stages, and switches enable selective connection of these segments based on the required time delay level, allowing a single unit to replace multiple monolithic custom designs

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250141101A1Phased array antenna with reconfigurable time delay units having external bypass connections and associated methods
Publication Date: 2025.05.01 EAGLE TECHNOLOGY LLC
  • US20250141101A1 patent drawing
  • US20250141101A1 patent drawing
  • US20250141101A1 patent drawing

AI summary

A phased array antenna may include an antenna substrate, an array of antenna elements carried by the antenna substrate, and time delay units (TDUs) coupled to the array of antenna element. Each time delay unit may include a circuit substrate, and delay circuits carried by the circuit substrate and coupled in series. Each delay circuit may have a respective signal delay value. At least one external bypass connection is carried by the circuit substrate and is coupled to the delay circuits to configure an overall time delay of the time delay unit.