Reconfigurable Trellis Decoder Architecture for Variable Viterbi Codes
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Solution Overview
Problem
Existing Viterbi decoders face challenges with exponential growth in memory, computational resources, and power consumption due to fixed decoding times and limited flexibility in handling varying constraint lengths and generator polynomials, restricting their application to specific types of Viterbi algorithms and parallelism levels.
Innovation Solution
A reconfigurable hardware architecture that enables fast on-line reconfiguration to decode both recursive and non-recursive systematic codes with varying constraint lengths and generator polynomials, utilizing radix-2 ACS butterflies and a shuffled trellis structure to minimize hardware requirements and power consumption, allowing for simultaneous implementation of multiple Viterbi decoding algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Viterbi decoding is implemented with fixed decoding time and specific constraint lengths, then decoding speed is improved, but hardware complexity and memory requirements grow exponentially
Solution Approach 1:
The patent implements dynamic reconfiguration capability that allows the decoder to adapt its constraint length and generator polynomial settings based on the specific coding scheme being used. This dynamic adaptation enables the hardware to optimize its structure for different decoding scenarios, avoiding the exponential growth of complexity by only allocating resources needed for the current configuration rather than supporting all possible configurations simultaneously
Solution Approach 2:
The system changes operational parameters such as constraint length K and generator polynomials dynamically based on the input signal characteristics and communication channel conditions. By adjusting these parameters rather than maintaining fixed high-capacity hardware for all scenarios, the decoder achieves high speed performance when needed while keeping hardware complexity manageable through parameter adaptation
2Reliability
If Viterbi decoders are designed for specific constraint lengths and generator polynomials, then decoding accuracy is improved, but adaptability to different coding schemes deteriorates
Solution Approach 1:
The patent designs a universal decoder architecture that can handle multiple coding schemes with different constraint lengths and generator polynomials through reconfiguration. The same hardware structure serves multiple functions by being dynamically adapted to different decoding requirements, achieving both high accuracy for specific schemes and broad adaptability across various coding standards without requiring separate dedicated decoders for each scheme
Solution Approach 2:
The decoder dynamically reconfigures its internal parameters and structure based on the detected coding scheme, allowing it to optimize its operation for each specific application while maintaining the ability to adapt to new schemes. This dynamic behavior enables the system to preserve decoding accuracy for each specific configuration while simultaneously achieving versatility across multiple coding standards
3Adaptability or versatility
If parallelism level is increased to handle varying constraint lengths, then decoding capability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic parallelism control where the degree of parallel processing is adjusted based on the specific decoding task requirements. For simpler decoding scenarios, fewer parallel processing units are activated, reducing power consumption. For more complex scenarios requiring higher adaptability, additional parallel units are engaged. This dynamic adjustment allows the system to achieve high decoding capability when needed while minimizing power consumption during normal operation
Data Source
AI summary
A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non-recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks, BMU generators and trace-back mechanisms for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.